CY7C1440KV33 datasheet(16/33 Pages) CYPRESS

Part #	CY7C1440KV33

Description	36-Mbit (1M 횞 36/2M 횞 18) Pipelined Sync SRAM (With ECC)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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16 / 33 page

CY7C1440KV33

CY7C1442KV33

CY7C1440KVE33

Document Number: 001-66676 Rev. *G

Page 16 of 33

3.3 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 3.3 V

Input rise and fall times (Slew Rate) ........................... 2 V/ns

Input timing reference levels ................. ........................1.5 V

Output reference levels ................. ...............................1.5 V

Test load termination supply voltage ............... .............1.5 V

3.3 V TAP AC Output Load Equivalent

2.5 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 2.5 V

Input rise and fall times (Slew Rate) ........................... 2 V/ns

Input timing reference levels ................. ......................1.25 V

Output reference levels ................ ..............................1.25 V

Test load termination supply voltage .................. ........1.25 V

2.5 V TAP AC Output Load Equivalent

TAP AC Switching Characteristics

Over the operating Range

Parameter [11, 12]

Description

Min

Max

Unit

Clock

tTCYC

TCK clock cycle time

50

–

ns

tTF

TCK clock frequency

–

20

MHz

tTH

TCK clock HIGH time

20

–

ns

tTL

TCK clock LOW time

20

–

ns

Output Times

tTDOV

TCK clock LOW to TDO valid

–

10

ns

tTDOX

TCK clock LOW to TDO invalid

0

–

ns

Set-up Times

tTMSS

TMS set-up to TCK clock rise

5

–

ns

tTDIS

TDI set-up to TCK clock rise

5

–

ns

tCS

Capture set-up to TCK rise

5

–

ns

Hold Times

tTMSH

TMS hold after TCK clock rise

5

–

ns

tTDIH

TDI hold after clock rise

5

–

ns

tCH

Capture hold after clock rise

5

–

ns

TDO

1.5V

20pF

Z = 50

Ω

O

50

Ω

TDO

1.25V

20pF

Z = 50

Ω

O

50

Ω

Notes

11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

12. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 2 V/ns (Slew Rate).

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