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CY7C1440KV33 Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY7C1440KV33 Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 33 page  CY7C1440KV33 CY7C1442KV33 CY7C1440KVE33 Document Number: 001-66676 Rev. *G Page 8 of 33 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.5 ns (250-MHz device). The CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 support secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.5 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. VSS Ground Ground for the core of the device. VSSQ I/O ground Ground for the I/O circuitry. VDDQ I/O power supply Power supply for the I/O circuitry. MODE Input-static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode pin has an internal pull-up. TDO JTAG serial output synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. TDI JTAG serial input synchronous Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TMS JTAG serial input synchronous Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG-clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M, NC/1G – No connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the die. Pin Definitions (continued) Name I/O Description |
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