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CY7C1440KV33 Datasheet(PDF) 32 Page - Cypress Semiconductor |
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CY7C1440KV33 Datasheet(HTML) 32 Page - Cypress Semiconductor |
32 / 33 page CY7C1440KV33 CY7C1442KV33 CY7C1440KVE33 Document Number: 001-66676 Rev. *G Page 32 of 33 Document History Page Document Title: CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33, 36-Mbit (1M × 36/2M × 18) Pipelined Sync SRAM (With ECC) Document Number: 001-66676 Rev. ECN Issue Date Orig. of Change Description of Change *E 4680535 04/10/2015 PRIT Changed status from Preliminary to Final. *F 4757974 05/07/2015 DEVM Updated Functional Overview: Updated ZZ Mode Electrical Characteristics: Changed maximum value of IDDZZ parameter from 89 mA to 75 mA. *G 5338013 07/05/2016 PRIT Updated Truth Table. Updated Neutron Soft Error Immunity: Updated values in “Typ” and “Max” columns corresponding to LSBU (Device without ECC) parameter. Updated to new template. |
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