CY7C1440KV25

Document Number: 001-94719 Rev. *D

Page 6 of 30

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

device).

The CY7C1440KV25 supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium processors. The burst

order is user selectable, and is determined by sampling the

MODE input. Accesses can be initiated with either the Processor

Address Strobe (ADSP) or the Controller Address Strobe

(ADSC). Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound burst

counter captures the first address in a burst sequence and

automatically increments the address for the rest of the burst

access.

Byte Write operations are qualified with the Byte Write Enable

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All writes are simplified with on-chip synchronous

self-timed Write circuitry.

asynchronous Output Enable (OE) provide for easy bank

HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

HIGH. The address presented to the address inputs (A) is stored

into the address advancement logic and the Address Register

while being presented to the memory array. The corresponding

data is allowed to propagate to the input of the Output Registers.

At the rising edge of the next clock the data is allowed to

propagate through the output register and onto the data bus

within 2.5 ns (250-MHz device) if OE is active LOW. The only

exception occurs when the SRAM is emerging from a deselected

state to a selected state, its outputs are always tristated during

the first cycle of the access. After the first cycle of the access,

the outputs are controlled by the OE signal. Consecutive single

Read cycles are supported. Once the SRAM is deselected at

clock rise by the chip select and either ADSP or ADSC signals,

its output will tristate immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions are

loaded into the address register and the address advancement

logic while being delivered to the memory array. The Write

this first cycle.

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the

corresponding address location in the memory array. If GW is

signals.

The CY7C1440KV25 provides Byte Write capability that is

described in the Write Cycle Descriptions table. Asserting the

Byte Write Enable input (BWE) with the selected Byte Write

not selected during a Byte Write operation will remain unaltered.

A synchronous self-timed Write mechanism has been provided

to simplify the Write operations.

Because CY7C1440KV25 is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQs inputs. Doing so will tristate the output drivers. As a

safety precaution, DQs are automatically tristated whenever a

Write cycle is detected, regardless of the state of OE.

MODE

Input-Static

or left floating selects interleaved burst sequence. This is a strap pin and should remain

static during device operation. Mode Pin has an internal pull-up.

TDO

JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

JTAG feature is not being utilized, this pin should be disconnected.

TDI

JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

TMS

JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

TCK

JTAG-Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must

NC

–

No Connects. Not internally connected to the die

NC/72M,NC/144M,

NC/288M, NC/576,

NC/1G

–

No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are

address expansion pins are not internally connected to the die.

Name

I/O

Description