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CY7C1440KV25 Datasheet(PDF) 23 Page - Cypress Semiconductor |
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CY7C1440KV25 Datasheet(HTML) 23 Page - Cypress Semiconductor |
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23 / 30 page  CY7C1440KV25 Document Number: 001-94719 Rev. *D Page 23 of 30 Figure 5. Write Cycle Timing [25, 26] Switching Waveforms (continued) tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE, BWX Data Out (Q) High-Z ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3) A2 A3 Data In (D) Extended BURST WRITE D(A2 + 2) Single WRITE tADH tADS tADH tADS t OEHZ t ADVH t ADVS tWEH tWES tDH tDS GW tWEH tWES Byte write signals are ignored for first cycle when ADSP initiates burst ADSC extends burst ADV suspends burst Notes 25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. |
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