CY7C1440KV25

Document Number: 001-94719 Rev. *D

Page 21 of 30

Switching Characteristics

Over the Operating Range

Parameter [18, 19]

Description

-250

Unit

Min

Max

1

–

ms

Clock

Clock Cycle Time

4.0

–

ns

Clock HIGH

1.5

–

ns

Clock LOW

1.5

–

ns

Output Times

Data Output Valid After CLK Rise

–

2.5

ns

Data Output Hold After CLK Rise

1.0

–

ns

Clock to Low Z [21, 22, 23]

1.0

–

ns

Clock to High Z [21, 22, 23]

–

2.6

ns

OE LOW to Output Valid

–

2.6

ns

OE LOW to Output Low Z [21, 22, 23]

0

–

ns

OE HIGH to Output High Z [21, 22, 23]

–

2.6

ns

Setup Times

Address Setup Before CLK Rise

1.2

–

ns

ADSC, ADSP Setup Before CLK Rise

1.2

–

ns

ADV Setup Before CLK Rise

1.2

–

ns

1.2

–

ns

Data Input Setup Before CLK Rise

1.2

–

ns

Chip Enable Setup Before CLK Rise

1.2

–

ns

Hold Times

Address Hold After CLK Rise

0.3

–

ns

ADSP, ADSC Hold After CLK Rise

0.3

–

ns

ADV Hold After CLK Rise

0.3

–

ns

0.3

–

ns

Data Input Hold After CLK Rise

0.3

–

ns

Chip Enable Hold After CLK Rise

0.3

–

ns

Notes

19. Test conditions shown in (a) of Figure 3 on page 20 unless otherwise noted.

be initiated.

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

High Z prior to Low Z under the same system conditions.

23. This parameter is sampled and not 100% tested.