CY7C1440KV25 datasheet(18/30 Pages) CYPRESS

Part #	CY7C1440KV25

Description	36-Mbit (1M 횞 36) Pipelined Sync SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C1440KV25

Document Number: 001-94719 Rev. *D

Page 18 of 30

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ............................... –65 °C to +150 °C

Ambient Temperature

with Power Applied .................................. –55 °C to +125 °C

Supply Voltage on VDD Relative to GND .....–0.5 V to +3.6 V

Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD

DC Voltage Applied to Outputs

in Tristate ..........................................–0.5 V to VDDQ + 0.5 V

DC Input Voltage ................................ –0.5 V to VDD + 0.5 V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ......................... > 2001 V

Latch-up Current ................................................... > 200 mA

Operating Range

Range

Ambient

Temperature

VDD

VDDQ

Industrial

–40 °C to +85 °C

2.5 V

+ 5%

2.5 V – 5%

to VDD

Neutron Soft Error Immunity

Parameter

Description

Test

Conditions Typ Max* Unit

LSBU

Logical

Single-Bit

Upsets

25 °C

<5

5

FIT/

Mb

LMBU

Logical

Multi-Bit

Upsets

25 °C

0

0.01 FIT/

Mb

SEL

Single Event

Latch up

85 °C

0

0.1

FIT/

Dev

* No LMBU or SEL events occurred during testing; this column represents a

statistical

2, 95% confidence limit calculation. For more details refer to Application

Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial

Failure Rates”.

Electrical Characteristics

Over the Operating Range

DC Electrical Characteristics

Over the Operating Range

Parameter [15, 16]

Description

Test Conditions

Min

Max

Unit

VDD

Power Supply Voltage

2.375

2.625

V

VDDQ

I/O Supply Voltage

for 2.5 V I/O

2.375

VDD

V

VOH

Output HIGH Voltage

for 2.5 V I/O, IOH = –1.0 mA

2.0

–

V

VOL

Output LOW Voltage

for 2.5 V I/O, IOL = 1.0 mA

–

0.4

V

VIH

Input HIGH Voltage[15]

for 2.5 V I/O

1.7

VDD + 0.3 V

V

VIL

Input LOW Voltage[15]

for 2.5 V I/O

–0.3

0.7

V

IX

Input Leakage Current except ZZ

and MODE

GND

 VI  VDDQ

–5

5

A

Input Current of MODE

Input = VSS

–30

–

A

Input = VDD

–5

A

Input Current of ZZ

Input = VSS

–5

–

A

Input = VDD

–30

A

IOZ

Output Leakage Current

GND

 VI  VDDQ, Output Disabled

–5

5

A

Notes

15. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).

16. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

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