CY7C1440KV25 datasheet(16/30 Pages) CYPRESS

Part #	CY7C1440KV25

Description	36-Mbit (1M 횞 36) Pipelined Sync SRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C1440KV25

Document Number: 001-94719 Rev. *D

Page 16 of 30

Identification Register Definitions

Instruction Field

CY7C1440KV25

(1M × 36)

Description

Revision Number (31:29)

000

Describes the version number.

Device Depth (28:24)

01011

Reserved for Internal Use

Architecture/Memory Type (23:18)

000000

Defines memory type and architecture

Bus Width/Density (17:12)

100111

Defines width and density

Cypress JEDEC ID Code (11:1)

00000110100

Allows unique identification of SRAM vendor.

ID Register Presence Indicator (0)

1

Indicates the presence of an ID register.

Scan Register Sizes

Register Name

Bit Size (× 36)

Instruction

3

Bypass

1

ID

32

Boundary Scan Order (165-ball FBGA package)

89

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures I/O ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces

all SRAM output drivers to a High Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does

not affect SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

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CY7C1440KV25 Datasheet(PDF) 16 Page - Cypress Semiconductor

CY7C1440KV25 Datasheet(HTML) 16 Page - Cypress Semiconductor

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