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CY7C1440KV25 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1440KV25
Description  36-Mbit (1M36) Pipelined Sync SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1440KV25 Datasheet(HTML) 1 Page - Cypress Semiconductor

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CY7C1440KV25
36-Mbit (1M × 36) Pipelined Sync SRAM
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-94719 Rev. *D
Revised June 30, 2016
36-Mbit (1M × 36) Pipelined Sync SRAM
Features
Supports bus operation up to 250 MHz
Available speed grade is 250 MHz
Registered inputs and outputs for pipelined operation
2.5-V core power supply
2.5-V I/O power supply
Fast clock-to-output times
2.5 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting interleaved or linear
burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single-cycle Chip Deselect
CY7C1440KV25 available in Pb-free 165-ball FBGA package.
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode Option
Functional Description
The CY7C1440KV25 SRAM integrates 1M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one, two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The CY7C1440KV25 operates from a +2.5 V core power supply
while all outputs may operate with a +2.5 V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Description
250 MHz
Unit
Maximum access time
2.5
ns
Maximum operating current
× 36
240
mA


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