CY7C1440KV25

Document Number: 001-94719 Rev. *D

Page 8 of 30

Truth Table

The truth table for CY7C1440KV25 follows. [1, 2, 3, 4, 5, 6]

Operation

DQ

Deselect Cycle, Power Down

None

H

X

X

L

X

L

X

X

X

L–H Tristate

Deselect Cycle, Power Down

None

L

L

X

L

L

X

X

X

X

L–H Tristate

Deselect Cycle, Power Down

None

L

X

H

L

L

X

X

X

X

L–H Tristate

Deselect Cycle, Power Down

None

L

L

X

L

H

L

X

X

X

L–H Tristate

Deselect Cycle, Power Down

None

L

X

H

L

H

L

X

X

X

L–H Tristate

Sleep Mode, Power Down

None

X

X

X

H

X

X

X

X

X

X

Tristate

READ Cycle, Begin Burst

External

L

H

L

L

L

X

X

X

L

L–H

Q

READ Cycle, Begin Burst

External

L

H

L

L

L

X

X

X

H

L–H Tristate

WRITE Cycle, Begin Burst

External

L

H

L

L

H

L

X

L

X

L–H

D

READ Cycle, Begin Burst

External

L

H

L

L

H

L

X

H

L

L–H

Q

READ Cycle, Begin Burst

External

L

H

L

L

H

L

X

H

H

L–H Tristate

READ Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

L

L–H

Q

READ Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

H

L–H Tristate

READ Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

L

L–H

Q

READ Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

H

L–H Tristate

WRITE Cycle, Continue Burst

Next

X

X

X

L

H

H

L

L

X

L–H

D

WRITE Cycle, Continue Burst

Next

H

X

X

L

X

H

L

L

X

L–H

D

READ Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

L

L–H

Q

READ Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

H

H

L–H Tristate

READ Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

L

L–H

Q

READ Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

H

L–H Tristate

WRITE Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

L

X

L–H

D

WRITE Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

L

X

L–H

D

Notes

1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care

for the remainder of the write cycle.

6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive

or when the device is deselected, and all data bits behave as output when OE is active (LOW).