CY7C1440KV25

Document Number: 001-94719 Rev. *D

Page 5 of 30

Pin Definitions

Name

I/O

Description

Input-Synchronous Address Inputs used to select one of the address locations. Sampled at the rising

active. A1:A0 are fed to the two-bit counter.

Input-Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the

SRAM. Sampled on the rising edge of CLK.

GW

Input-Synchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,

BWE).

BWE

Input-Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal

must be asserted LOW to conduct a byte write.

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment

the burst counter when ADV is asserted LOW, during a burst operation.

Input-Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

Input-Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

new external address is loaded.

Input-Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

only when a new external address is loaded.

OE

Input-Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.

When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated,

and act as input data pins. OE is masked during the first clock of a read cycle when

emerging from a deselected state.

ADV

Input-Synchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When

asserted, it automatically increments the address in a burst cycle.

ADSP

Input-Synchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both

ADSC

Input-Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

registers. A1:A0 are also loaded into the burst counter. When ADSP and ADSC are both

asserted, only ADSP is recognized.

ZZ

Input-Asynchronous ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a

non-time-critical “sleep” condition with data integrity preserved. For normal operation, this

pin has to be LOW or left floating. ZZ pin has an internal pull-down.

DQs, DQPs

I/O-Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the read cycle. The direction

of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.

Power Supply

Power supply inputs to the core of the device.

Ground

Ground for the core of the device.

I/O Ground

Ground for the I/O circuitry.

I/O Power Supply Power supply for the I/O circuitry.