6.42

IDT70V25S/L

High-Speed 8K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

15

Timing Waveform of Write with BUSY

Waveform of BUSY Arbitration Cycle Controlled by Address Match

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

2944 drw 13

R/

R/

(2)

(3)

(1)

,

NOTES:

1.

BUSY input (slave) and output (master).

2.

3.

2944 drw 14

ADDRESSES MATCH

(2)

2944 drw 15

ADDRESS "N"

(2)

MATCHING ADDRESS "N"