6.42

IDT70V25S/L

High-Speed 8K x 16 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

8

AC Electrical Characteristics Over the

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2.

This parameter is guaranteed by device characterization, but is not production tested.

3.

To access RAM,

4.

'X' in part number indicates power rating (S or L).

70V25X15

Com'l Only

70V25X20

Com'l

& Ind

70V25X25

Com'l

& Ind

Unit

Symbol

Parameter

Min.Max.Min.Max.

Min.

Max.

READ CYCLE

Read Cycle Time

15

____

20

____

25

____

ns

Address Access Time

____

15

____

20

____

25

ns

Chip Enable Access Time

(3)

____

15

____

20

____

25

ns

Byte Enable Access Time

(3)

____

15

____

20

____

25

ns

Output Enable Access Time

(3)

____

10

____

12

____

13

ns

Output Hold from Address Change

3

____

3

____

3

____

ns

Output Low-Z Time

(1,2)

3

____

3

____

3

____

ns

Output High-Z Time

(1,2)

____

10

____

12

____

15

ns

0

____

0

____

0

____

ns

Chip Disable to Power Down Time

(1,2)

____

15

____

20

____

25

ns

Semaphore Flag Update Pulse (

OE or SEM)10

____

10

____

10

____

ns

____

15

____

20

____

25

ns

2944 tbl 11a

70V25X35

Com'l

& Ind

70V25X55

Com'l

& Ind

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

READ CYCLE

Read Cycle Time

35

____

55

____

ns

Address Access Time

____

35

____

55

ns

Chip Enable Access Time

(3)

____

35

____

55

ns

____

35

____

55

ns

____

20

____

30

ns

Output Hold from Address Change

3

____

3

____

ns

Output Low-Z Time

(1,2)

3

____

3

____

ns

Output High-Z Time

(1,2)

____

15

____

25

ns

Chip Enable to Power Up Time

(1,2)

0

____

0

____

ns

Chip Disable to Power Down Time

(1,2)

____

35

____

50

ns

Semaphore Flag Update Pulse (

OE or SEM)15

____

15

____

ns

Semaphore Address Access

(3)

____

35

____

55

ns

2944 tbl 11b