Soft-Start Capacitance (nF)

0

2

4

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8

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12

0

100

200

300

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D007

ss

ss

ss

ref

t

(ms)

I

(µA)

C

(nF)

V

(V)

0.8

´

=

´

O

V

0.8 (V)

R1 R2

0.8 (V)

-

=

´

13

TPS65321A-Q1

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SLVSE55 – NOVEMBER 2017

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Feature Description (continued)

where

•

(1)

7.3.1.8 Soft-Start Pin (SS)

The TPS65321A-Q1 buck regulator regulates the output voltage by referencing the lower of either the internal

voltage reference or the SS pin voltage. A capacitor on the SS pin to ground implements a soft-start time. The

TPS65321A-Q1 buck regulator has an internal pullup current source of 2 μA that charges the external soft-start

than 1 nF.

where

•

•

(2)

To secure a smooth power up with effective soft-start, the delay between a shutdown event and a consecutive

power-up event (such as recovering from a UVLO event or from a thermal shutdown event) must be long enough

to allow a complete discharge of the soft-start capacitor. The soft-start capacitor is discharged through an internal

FET when the buck is disabled (EN1 = low). Because the FET has a finite resistance, a minimum disable time is

required to allow discharge of the capacitor. In either case, the buck must be disabled for at least 100 μs. For

soft-start capacitance with values higher than 1.5 nF, the discharge time of the capacitor increases linearly as

shown in Figure 8.

Figure 8. Soft-Start Capacitance Value versus Discharge Time

7.3.1.9 Reset Output, nRST

The nRST pin pf the TPS65321A-Q1 is a open-drain output between the nRST pin and the GND pin. The power-

on-reset output asserts low until the output voltage on the FB1 pin exceeds the setting thresholds (91%) and the

deglitch timer has expired. Additionally, whenever the EN1 pin is low or open, nRST immediately asserts low

regardless of the output voltage. If a thermal shutdown occurs because of excessive thermal conditions, this pin

also asserts low. When the nRST is released (not asserted low) an external resistor connected to any external

bias voltage pulls up this nRST pin.