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TPS65321A-Q1 Datasheet(PDF) 29 Page - Texas Instruments |
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TPS65321A-Q1 Datasheet(HTML) 29 Page - Texas Instruments |
29 / 43 page ![]() Ambient Temperature (qC) 0.5 125 150 1 100 1.5 75 2 2.5 3 25 50 0 0 29 TPS65321A-Q1 www.ti.com SLVSE55 – NOVEMBER 2017 Product Folder Links: TPS65321A-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 8.2.1.2.12 Power Dissipation Losses of the LDO Regulator PLDO = (VVIN_LDO – V(LDO_OUT)) × I(LDO_OUT) (45) 8.2.1.2.13 Total Device Power Dissipation Losses and Junction Temperature 1. Supply loss: PIC = VI × IQ-normal (46) 2. Total power loss: PTotal = PCON + PSW + PGate + PLDO + PIC (47) For a given operating ambient temperature TA: TJ = TA + Rth × PTotal where • TJ is the junction temperature in °C • TA is the ambient temperature in °C • Rth is the thermal resistance of package in (°C/W) • PTotal is the total power dissipation (W) (48) For a given maximum junction temperature TJ-max = 150°C, the allowed Total power dissipation is given as: TA-max = TJ-max -Rth × PTotal (49) where • TA-max is the maximum ambient temperature in °C • TJ-max is the maximum junction temperature in °C (50) Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the Schottky diode, and trace resistance that impact the overall efficiency of the regulator. Figure 17 shows the thermal derating profile of the 14-pin HTSSOP Package With PowerPAD™ . It is important to consider additional cooling strategies if necessary to maintain the junction temperature of the device below the maximum junction temperature of 150 °C. Figure 17. Thermal Derating Profile ofTPS65321A-Q1 in 14-pin HTSSOP Package With PowerPAD |
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