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TPS65321A-Q1 Datasheet(PDF) 16 Page - Texas Instruments |
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TPS65321A-Q1 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 43 page  PLL RT/CLK External Clock Source Rfset 4 k 50 10 …F 16 TPS65321A-Q1 SLVSE55 – NOVEMBER 2017 www.ti.com Product Folder Links: TPS65321A-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Feature Description (continued) When the buck regulator transitions from the PLL mode to the resistor mode, the switching frequency slows down from the CLK frequency to 150 kHz, then reapplies the 0.5-V voltage. The resistor then sets the switching frequency. The switching-frequency divisor changes to 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on the FB1 pin. The buck regulator implements a digital frequency shift to enable synchronizing to an external clock during standard start-up and fault conditions. Figure 10. Synchronizing to a System Clock 7.3.1.15 Overvoltage Transient Protection The TPS65321A-Q1 buck regulator incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power-supply designs with low-value output capacitance. For example, with the buck regulator output overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the FB1 pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error amplifier output to a high voltage, thus requesting the maximum output current. On removal of the condition, the buck regulator output rises and the error-amplifier output transitions to the steady-state duty cycle. In some applications, the buck regulator output voltage can respond faster than the error-amplifier output can respond which leads to possible output overshoot. The OVTP feature minimizes the output overshoot when using a low- value output capacitor by implementing a circuit to compare the FB1-pin voltage to the OVTP threshold (which is 109% of the internal voltage reference). The FB1 pin voltage exceeding the OVTP threshold disables the high- side MOSFET, preventing current from flowing to the output and minimizing output overshoot. The FB1 voltage dropping lower than the OVTP threshold allows the high-side MOSFET to turn on at the next clock cycle. 7.3.1.16 Small-Signal Model for Loop Response Figure 11 shows an equivalent model for the buck-regulator control loop which can be modeled in a circuit- simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmea of 310 μS. Model the error amplifier using an ideal voltage-controlled current source. Resistor, RO, and capacitor, CO, model the open-loop gain and frequency response of the amplifier. The 1-mV AC-voltage source between nodes a and b effectively breaks the control loop for the frequency-response measurements. Plotting c versus a shows the small-signal response of the frequency compensation. Plotting a versus b shows the small-signal response of the overall loop. Check the dynamic loop response by replacing RL with a current source that has the appropriate load-step amplitude and step rate in a time-domain analysis. This equivalent model is only valid for continuous-conduction-mode designs. |
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