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TPS65321A-Q1 Datasheet(PDF) 14 Page - Texas Instruments |
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TPS65321A-Q1 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 43 page  L dc O d S on I L hs d (I R V V ) 1 ƒ (max skip) t (V I R V ) æ ö æ ö ´ + + = ´ ç ÷ ç ÷ - ´ + è ø è ø T 1.0888 S 206033 R (k ) ƒ (kHz) W = 14 TPS65321A-Q1 SLVSE55 – NOVEMBER 2017 www.ti.com Product Folder Links: TPS65321A-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Feature Description (continued) 7.3.1.10 Overload-Recovery Circuit The TPS65321A-Q1 buck regulator has an overload recovery (OLR) circuit. The OLR circuit soft-starts the output from the overload voltage to the nominal regulation voltage on removal of the fault condition. The OLR circuit discharges the SS pin to a voltage slightly greater than the FB1 pin voltage using an internal pulldown of 382 μA when the error amplifier changes to a high voltage from a fault condition. On removal of the fault condition, the output soft starts from the fault voltage to nominal output voltage. 7.3.1.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS65321A-Q1 buck regulator is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is 0.5 V (typical) and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 3 or the curves in Figure 2. To reduce the solution size, the user typically sets the switching frequency as high as possible. However, consider tradeoffs of the supply efficiency, maximum input voltage, and minimum controllable on-time. The minimum controllable on-time is 100 ns (typical) and limits the maximum operating input voltage. The frequency-shift circuit also limits the maximum switching frequency. The following sections discuss more details of the maximum switching frequency. (3) 7.3.1.12 Overcurrent Protection and Frequency Shift The TPS65321A-Q1 buck regulator implements current-mode control, which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. During each cycle, the switch current and COMP pin voltage are compared. When the peak-switch current intersects the COMP voltage, the high-side switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. Internal clamping of the error-amplifier output functions as a switch current-limit. The TPS65321A-Q1 buck regulator also implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on the FB1 pin. During short-circuit events (particularly with high-input-voltage applications), the control loop has a finite minimum controllable on-time, and the output has a low voltage. During the switch on-time, the inductor current ramps to the peak current-limit because of the high input voltage and minimum on-time. During the switch off-time, the inductor typically does not have enough off- time and output voltage for the inductor to ramp down by the ramp-up amount. The frequency shift effectively increases the off-time which allows the current to ramp down. 7.3.1.13 Selecting the Switching Frequency The switching frequency that is selected must be the lower value of the two equations, Equation 4 and Equation 5. Equation 4 is the maximum switching-frequency limitation set by the minimum controllable on-time. Setting the switching frequency above this value causes the regulator to skip switching pulses. The device maintains regulation, but pulse-skipping leads to high inductor current and a significant increase in output ripple voltage. Use Equation 5 to calculate the maximum switching frequency limit set by the frequency-shift protection. For adequate output short-circuit protection at high input voltages, set the switching frequency to a value less than the ƒS(maxshift) frequency. In Equation 5, to calculate the maximum switching frequency one must take into account that the output voltage decreases from the nominal voltage to 0 volts, and the ƒdiv integer increases from 1 to 8 corresponding to the frequency shift. where • IL = inductor current • Rdc = inductor resistance • VI = maximum input voltage |
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