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NCP81243 Datasheet(PDF) 22 Page - ON Semiconductor |
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NCP81243 Datasheet(HTML) 22 Page - ON Semiconductor |
22 / 26 page ![]() NCP81243 www.onsemi.com 22 PWM Comparators The noninverting input of the comparator for each phase is connected to the summed output of the error amplifier (COMP) and each phase current (IL*DCR*Phase Balance Gain Factor). The inverting input is connected to the oscillator ramp voltage with a 1.3 V offset. The operating input voltage range of the comparators is from 0 V to 3.0 V and the output of the comparator generates the PWM output. During steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. The steady state duty cycle is still calculated by approximately Vout/Vin. During a transient event, the controller will operate in a hysteretic mode with the duty cycles pull in for all phases as the error amp signal increases with respect to all the ramps. Phase Detection Sequence Normally, NCP81243 operates as a 3−phase VCORE/ 2−phase Auxiliary PWM controller however the NCP81243 can also be configures as a 4+1−phase controller. During start−up, the number of operational phases and their phase relationship is determined by the internal circuitry monitoring the CSP outputs. Configuration Phase Configuration Programming Pin Phase Config (30 mv/us slew rate) Programming Pin CSPx Unused Pins 1 4+1 80k6 All CSP pins connected normally 2 4+0 80k6 Connect CSP1A to VCC through a 2 k resistor. All other CSP pins connected normally Float:PWM1A, ILIMA, DIFFOUTA,COMPA,CSCOMPA Ground: IOUTA, FBA, CSSUMA, CSREFA,VSPA, TsenseA 3 3+2 13k All CSP pins connected normally No unused pins 4 3+1 13k Connect CSP2A to VCC through a 2k resistor. All other CSP pins connected normally Float: PWM2A 5 3+0 13k Connect CSP2A and CSP1A to VCC through a 2k resistor. All other CSP pins connected normally Float: PWM2A, PWM1A, ILIMA, DIFFOUTA, COMPA, CSCOMPA Ground: IOUTA, FBA, CSSUMA, CSREFA, VSPA, TsenseA 6 2+2 13k Connect CSP3 to VCC through a 2k resistor pulled to VCC. All other CSP pins connected normally Float: PWM3 7 2+1 13k Connect CSP2A to VCC through a 2k resistor. All other CSP pins connected normally Float PWM3, PWM2A 8 2+0 13K Connect CSP3, CSP2A and CSP1A to VCC through a 2k resistor. All other CSP pins connected normally Float PWM3, PWM1A, PWM2A, PWM3ILIMA, DIFFOUTA, COMPA, CSCOMPA Ground: IOUTA, FBA, CSSUMA, CSREFA, VSPA, TsenseA 9 1+2 13K Connect CSP3 and CSP2 through a 2k resistor pulled to VCC. All other CSP pins connected normally Float: PWM2 and PWM3 10 1+1 13K Connect CSP3, CSP2 and CSP2A through a 2k resistor pulled to VCC. All other CSP pins connected normally Float: PWM2, PWM3, PWM2A 11 1+0 13K Connect CSP3, CSP2, CSP2A and CSP1A through a 2k resistor pulled to VCC. All other CSP pins connected normally Float: PWM2, PWM3, PWM1A, PWM2A, ILIMA, DIFFOUTA, COMPA, CSCOMPA Ground: IOUTA, FBA, CSSUMA, CSREFA, VSPA, VSNA The PWM outputs are logic−level devices intended for driving fast response external gate drivers such as the NCP81151 and NCP81161. As each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one PWM output can be on at the same time to allow overlapping phases. |
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