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TPA3220

SLASEN3 – JANUARY 2018

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Copyright © 2018, Texas Instruments Incorporated

8 Parameter Measurement Information

All parameters are measured according to the conditions described in the Recommended Operating Conditions.

Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to

out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to

use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10

Ω + 47 nF) can

be used to reduce the out of band noise remaining on the amplifier outputs.

9 Detailed Description

9.1 Overview

TPA3220 is designed as a feature-enhanced cost efficient high power Class-D audio amplifier. It has built-in

advanced protection circuitry to ensure maximum product robustness as well as a flexible feature set including

built in LDO for easy supply of low voltage circuitry, selectable gain, switching frequency, master/slave

synchronization of multiple devices, selectable PWM modulation scheme, mute function, temperature and

clipping status signals. TPA3220 has a bandwidth up to 100 kHz and low output noise designed for high

resolution audio applications and accepts both differential and single ended analog audio inputs at levels from 1

power supply between 7 V and 30 V.

To facilitate system design, the TPA3220 needs only a (typical) 30 V power stage supply. The TPA3220 has an

internal voltage regulator supplied from the VDD pin for the analog and digital system blocks and the output

stage gate drive respectively. The VDD pin can be connected directly to PVDD in case of only this power supply

rail being available.

To reduce device power losses an external 5 V supply can be used for the AVDD and VDD supply pins. The

internal voltage regulator connected to the VDD pin is automatically turned off if an external 5 V supply is used

for this pin. Although supplied from the same 5 V source, separating AVDD and VDD on the printed-circuit board

(PCB) by RC filters (see application diagram for details) is recommended. These RC filters provide the

recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as

close to their associated pins as possible. In general, the physical loop with the power supply pins, decoupling

capacitors and GND return path to the device pins must be kept as short as possible and with as little area as

possible to minimize induction (see Layout Examples for additional information).

The floating supplies for the output stage high side gate drives are supplied by built-in bootstrap circuitry

requiring only an external capacitor for each half-bridge.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap

pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential

and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33 nF ceramic

capacitors, size 0603 or 0805, for the bootstrap supply. These 33 nF capacitors ensure sufficient energy storage,

even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during

the remaining part of the PWM cycle.

Special attention should be paid to the power stage power supply; this includes component selection, PCB

placement, and routing.

For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X

node is decoupled with 1 μF ceramic capacitors placed as close as possible to the PVDD supply pins. It is

recommended to follow the PCB layout of the TPA3220 reference design. For additional information on

recommended power supply and required components, see the application diagrams in this data sheet.

If using external power supply for the AVDD and VDD internal regulators, this supply should be from a low-noise,

low-output-impedance voltage regulator. Likewise, the 30 V power stage supply is assumed to have low output

impedance throughout the entire audio band, and low noise. The power supply sequence is not critical as

facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power supply

is settled for minimum turn on audible artefacts. Moreover, the TPA3220 is fully protected against erroneous

power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are noncritical within

the specified range (see the Recommended Operating Conditions table of this data sheet).