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TPA3220

SLASEN3 – JANUARY 2018

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Copyright © 2018, Texas Instruments Incorporated

(1)

VDD must be connected to a supply of 5V in LDO bypass mode; OR 7V to 30V with LDO active. VDD can be connected directly to

PVDD in LDO bypass mode, but must not exceed PVDD voltage.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

PVDD

Power-stage supply

DC supply voltage

7

30

32

V

Supply voltage for internal LDO regulator

to supply GVDD and AVDD

DC supply voltage

7

32

V

External supply for VDD, GVDD and

AVDD. Internal LDO bypassed

DC supply voltage

4.5

5

5.5

V

AVDD

Supply voltage for analog circuits

DC supply voltage

4.5

5

5.5

V

GVDD

Supply voltage for gate-drive circuitry

DC supply voltage

4.5

5

5.5

V

Output filter inductance

5

10

μH

Output filter inductance, PBTL before the

LC filter

5

10

Output filter inductance, PBTL after the

LC filter

each inductor

5

10

PWM frame rate selectable for AM

interference avoidance; 1% Resistor

tolerance

Nominal

575

600

625

kHz

AM1

510

533

555

AM2

460

480

500

PWM frame rate programming resistor

Nominal; Master mode

49.5

50

50.5

k

Ω

AM1; Master mode

29.7

30

30.3

AM2; Master mode

9.9

10

10.1

PVDD close decoupling capacitors

1.0

μF

Voltage on FREQ_ADJ pin for slave

mode operation

Slave Mode (Connect to AVDD)

5

V

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

TPA3220

UNIT

DDW 44-PINS HTSSOP

JEDEC STANDARD 4 LAYER PCB

Junction-to-ambient thermal resistance

23.5

°C/W

Junction-to-case (top) thermal resistance

11.1

°C/W

Junction-to-board thermal resistance

4.5

°C/W

Junction-to-top characterization parameter

0.2

°C/W

Junction-to-board characterization parameter

4.5

°C/W

Junction-to-case (bottom) thermal resistance

1.1

°C/W