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TPA3220

SLASEN3 – JANUARY 2018

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Copyright © 2018, Texas Instruments Incorporated

(1)

I=Input, O=Output, I/O= Input/Output, P=Power

Pin Functions

NAME

NO.

I/O

(1)

DESCRIPTION

HEAD

11

I

0 = AD, 1 = HEAD. Refer to: AD-Mode and HEAD-Mode PWM Modulation

AVDD

21

P

AVDD voltage supply. Refer to: Internal LDO, AVDD and GVDD Supplies

BST1_M

43

P

OUT1_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_M required.

Refer to: BST capacitors

BST1_P

44

P

OUT1_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_P required.

Refer to: BST capacitors

BST2_M

23

P

OUT2_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_M required.

Refer to: BST capacitors

BST2_P

24

P

OUT2_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_P required.

Refer to:BST capacitors

CMUTE

17

P

Mute and Startup Timing Capacitor

Refer to: Device Reset

FAULT

4

O

Shutdown signal, open drain; active low

Refer to: Error Reporting, Error Reporting

FREQ_ADJ

14

O

Oscillator frequency programming pin

Refer to: Oscillator

GAIN/SLV

2

I

Closed loop gain and master/slave programming pin.

Input Configuration, Gain Setting And Master / Slave OperationRefer to:

GND

5, 6, 7, 18, 19,

20, 25, 26, 33,

34, 41, 42

P

Ground

GVDD

22

P

Gate drive supply. Refer to: Internal LDO, AVDD and GVDD Supplies

IN1_M

9

I

Negative audio input for channel 1

IN1_P

8

I

Positive audio input for channel 1

IN2_M

16

I

Negative audio input for channel 2

IN2_P

15

I

Positive audio input for channel 2

OSCM

12

I/O

Oscillator synchronization interface.

Refer to: Input Configuration, Gain Setting And Master / Slave Operation

OSCP

13

I/O

Oscillator synchronization interface

Refer to: Input Configuration, Gain Setting And Master / Slave Operation

OUT1_M

3

O

Negative output for channel 1

OTW_CLIP

35

O

Clipping warning and Over-temperature warning; open drain; active low.

Refer to: Error Reporting

OUT1_P

39, 40

O

Positive output for channel 1

OUT2_M

27, 28

O

Negative output for channel 2

OUT2_P

32

O

Positive output for channel 2

PVDD

29, 30, 31, 36,

37, 38

P

PVDD supply. Refer to: PVDD Capacitor Recommendation, PVDD Supply

RESET

10

I

Device reset Input; active low. Refer to: Fault Handling, Powering Up, Powering Down

VDD

1

P

Input power supply. Refer to: Internal LDO, VDD Supply

PowerPad™

P

Ground, connect to PCB copper pour. Placed on bottom side of device

(1)

X refers to inputs connected through AC coupling capacitor, 0 refers to logic low (GND), 1 refers to logic high (AVDD).

(2)

2N refers to differential input signal, 1N refers to single ended input signal. +1 refers to number of logic control (RESET) input pins.

Table 1. Mode Selection Pins

OUTPUT

CONFIGURATION

DESCRIPTION

IN2_M

IN2_P

HEAD

X

X

0

1N/2N + 1

2 × BTL

Stereo, BTL output configuration, AD mode modulation

X

X

1

1N/2N + 1

2 × BTL

Stereo, BTL output configuration, HEAD mode modulation

0

0

0

1N/2N + 1

1 x PBTL

Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P

and OUT1_M to OUT2_M, AD mode modulation

0

0

1

1N/2N + 1

1 x PBTL

Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P

and OUT1_M to OUT2_M, HEAD mode modulation

1

1

0

1N/2N + 1

1 x BTL

Mono, BTL configuration. OUT1_M and OUT1_P active, AD mode

modulation

1

1

1

1N/2N + 1

1 x BTL

Mono, BTL configuration. OUT1_M and OUT1_P active, HEAD mode

modulation