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TPA3220

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SLASEN3 – JANUARY 2018

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Copyright © 2018, Texas Instruments Incorporated

9.4.5.3 DC Speaker Protection

The output DC protection scheme protects a speaker from excess DC current in case one terminal of the

speaker is connected to the amplifier while the other is accidentally shorted to the chassis ground. Such a short

circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current

levels. The output DC protection detects any unbalance of the output and input current of a BTL or PBTL output

configuration (current into/out of one half-bridge equals current out of/into the other half-bridge), and in the event

of the unbalance exceeding a programmed threshold, the overload counter increments until its maximum value

and the affected output channel is shut down. DC Speaker Protection is enabled in both BTL and PBTL mode

operation.

9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage in the case that a power output pin

(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent

after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is

performed at startup after RESET is pulled high. When PPSC detection is activated by a short on the output, all

half-bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence

and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that

there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to

PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The

typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low. If no shorts are

present the PPSC detection passes, and FAULT is released. A device reset will start a new PPSC detection.

PPSC detection is enabled in both BTL and PBTL output configurations. To make sure not to trip the PPSC

detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.

9.4.5.5 Overtemperature Protection OTW and OTE

TPA3220 has a two-level temperature-protection system that asserts an active-low warning signal (OTW_CLIP)

when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds

155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-

impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,

RESET must be asserted. Thereafter, the device resumes normal operation.

9.4.5.6 Undervoltage Protection (UVP), Overvoltage Protection (OVP) and Power-on Reset (POR)

The UVP, OVP and POR circuits of the TPA3220 fully protect the device in any power-up/down, and brownout

situation, and also in overvoltage situation with PVDD not exceeding the values stated in Absolute Maximum

Ratings. While powering up, the POR circuit ensures that all circuits are fully operational when the AVDD supply

voltage reaches the value stated in the Electrical Characteristics table. Although AVDD is independently

monitored, a supply voltage drop below the UVP threshold on AVDD pin results in all half-bridge outputs

immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device

automatically resumes operation when all supply voltages have increased above their UVP threshold. In case of

an OVP event, all half-bridge outputs are immediately set in the high-impedance (Hi-Z) state and FAULT is

asserted low until PVDD is below the OVP threshold.