PVDD

RESET

GVDD

FAULT

AVDD

VIN_X

OUT_X

VOUT_X

C 20ms

VDD

V_CMUTE

20

TPA3220

SLASEN3 – JANUARY 2018

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Copyright © 2018, Texas Instruments Incorporated

Figure 21. Startup Timing

When RESET is released to turn on TPA3220, FAULT signal will turn low and AVDD voltage regulator will be

enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the

Electrical Characteristics table of this data sheet). After a pre-charge time to stabilize the DC voltage across the

input AC coupling capacitors, the ramp up sequence starts and completes once the CMUTE node is charged to

its final value.

9.4.1.1 Startup Ramp Time

During the startup ramp the CMUTE capacitor is charged by an internal current generator. With use of the

recommended 33 nF CMUTE capacitor value, the startup ramp time is approximately 20 ms. Higher CMUTE

capacitor value will increase the ramp time, and a lower value will decrease the ramp time. The recommended

CMUTE capacitor value is selected for minimum audible artifacts during startup and shutdown ramp.

9.4.2 Powering Down

The TPA3220 does not require a power-down sequence. The device remains fully operational as long as the

VDD, AVDD and PVDD voltages are above their undervoltage protection (UVP) voltage thresholds (see the

Electrical Characteristics table of this data sheet). Although not specifically required, it is a good practice to hold

RESET low during power down, thus preventing audible artifacts including pops or clicks by initiating a controlled

ramp down sequence of the output voltage. The ramp down sequence will complete once the CMUTE node is

discharged.

9.4.2.1 Power Down Ramp Time

During the power down ramp the CMUTE capacitor is discharged by internal circuitry. With use of the

recommended 33 nF CMUTE capacitor value, the power-down ramp time is approximately 20 ms.