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K4N26323AE Datasheet(PDF) 22 Page - Samsung semiconductor |
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K4N26323AE Datasheet(HTML) 22 Page - Samsung semiconductor |
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22 / 52 page  - 22 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the GDDR2 SDRAM, the CAS timing accepts one extra address, column address A8, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A8 is low when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A8 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge com- mand may be issued with any read or write command. Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle. When the Data Mask is activated (DM high) during write operation the write data is masked immediately (DM to Data-mask Latency is zero). DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge. DM FUNCTION DM masked by DM=H CMD NOP NOP NOP NOP NOP NOP DQ’s NOP CK, CK 02 1 345 6 9 WRITE A Posted CAS Precharge A tWR = 5 DINA0 DINA2 DINA3 DQS DINA1 WL = 2 |
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