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K4N26323AE Datasheet(PDF) 18 Page - Samsung semiconductor |
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K4N26323AE Datasheet(HTML) 18 Page - Samsung semiconductor |
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18 / 52 page  - 18 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC Burst Write Operation The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by an Additive Latency(AL) plus one and is equal to (AL + 1). The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the clock and at the first falling edge of the clock. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the clock until the burst length of 4 is com- pleted. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR). Burst Write Operation : AL= 1, CL = 7, WL = 2, tWR = 5 CMD Posted CAS NOP NOP NOP NOP NOP DQ NOP CK, CK 1 02 3 4 5 6 9 WL =2 Precharge WRITE A CMD DQ CK, CK DQS CL = 7 tWL = 1 Burst Write followed by Burst Read : RL = 7 (AL=0, CL=7), WL = 1, tCDLR = 4 The minimum number of clock from the burst write command to the burst read command is WL+2+a write-to- read-turn-around-time(tCDLR). 02 3 14 15 16 NOP NOP NOP NOP NOP NOP NOP Post CAS READ A Write to Read Latency = WL + 2 + t CDLR =7 NOP > = tCDLR DINA0 DINA1 DINA2 DINA3 DINA0 DINA1 DINA2 DINA3 DOUTA0 DOUTA1 DOUTA2 DOUTA3 DQS Post CAS WRITE A 1 7 NOP tWR = 5 |
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