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K4N26323AE Datasheet(PDF) 7 Page - Samsung semiconductor |
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K4N26323AE Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 52 page ![]() - 7 - Rev. 1.7 (Jan. 2003) 128M GDDR2 SDRAM K4N26323AE-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both direc- tions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM0 ~DM3 Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM pins are input only, the DM loading matches the DQ and DQS loading. BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 - A11 Input Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands. DQ Input/ Output Data Input/ Output: Bi-directional data bus. DQS0~ DQS3 DQS0~ DQS3 Input/ Output Data Strobe: output with read data, input with write data for source synchronous operation.Edge-aligned with read data, centered in write data. DQS Scheme Differential DQS per byte DQS0, DQS0 DQS0 for DQ0-DQ7 DQS1, DQS1 DQS1 for DQ8-DQ15 DQS2, DQS2 DQS2 for DQ16-DQ23 DQS3, DQS3 DQS3 for DQ24-DQ31 NC/ RFU No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.8V ± 0.1V VSSQ Supply DQ Ground VDD Supply Power Supply: 2.5V ± 0.1V VSS Supply Ground VREF Supply Reference voltage: half Vddq , 2 Pins : (M,2) for Data input , (M,13) for CMD and ADDRESS ZQ input Resistor connection pin for On-die termination. The value of Resistor = 2 X (target value (Rterm) of termination resistance of DQ pin of each chip) |
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