K4N26323AE datasheet(36/52 Pages) SAMSUNG

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K4N26323AE Datasheet(PDF) 36 Page - Samsung semiconductor

Part #	K4N26323AE

Description	128Mbit GDDR2 SDRAM

Download	52 Pages

Scroll/Zoom	100%

Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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36 / 52 page

- 36 -

Rev. 1.7 (Jan. 2003)

128M GDDR2 SDRAM

K4N26323AE-GC

Note 1 :

- The JEDEC DDR-II specification currently defines the output data valid window(tDV) as the time period when the data

strobe and all data associated with that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case

output valid window even then the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle

variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

tQH Timing (CL7, BL4)

tHP

CK, CK

DQS

COMMAND

READA

tQH

Da0

tDQSQ(max)

Da1

Da2

Da3

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