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September 11, 2000

IDT77105

Interrupt Status

Interrupt Status

Interrupt Status

Interrupt Status

Address: 0x01

Address: 0x01

Address: 0x01

Address: 0x01

Diagnostic Control

Diagnostic Control

Diagnostic Control

Diagnostic Control

Address: 0x02

Address: 0x02

Address: 0x02

Address: 0x02

Master Type Initial State

Function

Bit 7

—

—

Reserved

Bit 6

R

0 = Bad Signal

Good Signal Bit See definition on pages 10 and 11.

1 = Good Signal

0 = Bad Signal

Bit 5

sticky

0

HEC Error

Interrupt sets when a HEC error is detected in a received cell.

Bit 4

sticky

0

"Short Cell" Received

Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected by the TC receiving Start-of-

Cell command bytes with fewer than 53 bytes between them.

Bit 3

sticky

0

Transmit Parity Error

If Bit 4 of Register 0x00 is set (Transmit Data Parity Check), this interrupt flags a transmit data parity error condition. Odd

parity is used.

Bit 2

sticky

0

Receive signal Condition Change This interrupt is set when the received 'signal' changes either from 'bad to good' or from

'good to bad'.

Bit 1

sticky

0

Received Symbol Error Set on receiving a cell with an undefined symbol.

Bit 0

sticky

0

Receive FIFO Overrun Interrupt sets to indicate when the receive FIFO has overflowed.

Master Type Initial State

Function

Bit 7

R/W

0 = normal

Force TxClav Deassert

Used during the loopback mode to prevent upstream system from continuing to send data to 77105.

Bit 6

R/W

0 = UTOPIA

RxClav Operation Select

The UTOPIA standard dictates that during cell mode operation, if the receive FIFO no longer has a complete cell available

for transfer from PHY, RxClav is deasserted following transfer of the last byte out of the PHY to the upstream system. With

this bit set, early deassertion of this signal will occur at the end of Payload byte 44 (as in octet mode for TxFull). This pro-

vides early indication to the upstream system of this impending condition.

"Standard UTOPIA RxClav" = 0

"Cell mode = Byte mode" = 1

Bit 5

R/W

0 = “multi-PHY”

Single/Multi-PHY Configuration Select

0 = Single-PHY mode: RxData, RxPrty and RxSOC never tri-state

1 = Multi-PHY mode:

RxEnb = 1 then tri-state RxData, RxPrty, RxSOC

Bit 4

R/W

0 = normal

RFLUSH = Clear Receive FIFO

This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC signals this completion by clearing this bit.

Bit 3

R/W

0 = normal

Insert Transmit Payload Error

Inserts cell payload errors in transmitted cells. This can be used to test error detection and recovery systems at destination

station, or, under loopback control, the local receiving station. This payload error is generated by flipping bit 0 of the last cell

payload byte.

Bit 2

R/W

0 = normal

Insert Transmit HEC Error

Insert HEC error in Byte 5 of cell. This can be used to test error detection and recovery systems in down-stream switches, or,

under loopback control, the local receiving station. This HEC error is generated by flipping bit 0 of the HEC byte.

Bit 1, 0

R/W

0 = normal

Loopback Control

bit# 1 0

0 0 Normal mode (receive from network)

0 1 Reserved

1 0 PHY Loopback

1 1 Line Loopback