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September 11, 2000

IDT77105

Figure 14 Multi-PHY Receive Waveform

PHY to Magnetics interface

PHY to Magnetics interface

PHY to Magnetics interface

PHY to Magnetics interface

Figure 21 provides the appropriate connection scheme to the Magnetics Module. The set of values provided will ensure the return Loss specifica-

tion is met.

Status and Control Register List

Status and Control Register List

Status and Control Register List

Status and Control Register List

Nomenclature

R/W = register may be read and written via the utility bus;

R-only or W-only = register may be read-only or write-only via the utility bus;

sticky = register bit is cleared after the register containing it is read.

“0” = ‘cleared’ or ‘not set’

“1” = ‘set’

Master Control Register

Master Control Register

Master Control Register

Master Control Register

Address: 0x00

Address: 0x00

Address: 0x00

Address: 0x00

Master Type Initial State

Function

Bit 7

R/W

0

UPLO

Controls pin 11, User Programmable Output Latch. Note that the polarity of pin 11 is opposite the polarity of this register bit.

Bit 6

R/W

0 = disabled

Discard Receive Error Cells

On receipt of any cell with an error (e.g. short cell, invalid symbol or HEC error (if enabled)), the cell will be discarded before

entering the receive FIFO.

Bit 5

R/W

0 = disabled

Enable Cell Error Interrupts Only

If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only ‘Received Cell Error’ to trigger an interrupt.

Received Cell Errors are: short cell, invalid symbol and HEC error.

Bit 4

R/W

0 = disabled

Transmit Data Parity Check

Enable checking of TxData[7:0] parity against TxParity.

Bit 3

R/W

1 = enabled

Discard Received Idle Cells

Enable discarding of received idle (VPI/VCI = 0) cells. There is no indication when such a discard takes place.

Bit 2

R/W

0 = disabled

Halt Tx

Halts transmission of data and forces both TxD+/- signals to a logic low state.

Bit 1

R/W

0 = cell mode

UTOPIA mode select:

0 = cell mode, 1 = byte mode.

Bit 0

R/W

1 = enabled

Enable Interrupt Pin (Interrupt Mask Bit)

Enables interrupt output pin. If cleared, INT (pin 53 is always high. If set, INT will drive low when an interrupt occurs.

RxClk

RxSOC

RxEnb

RxData

H1

H2

P48

X

3445 drw 17

H1

RxClav

X

X

Z

Z