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IDT77105 Datasheet(PDF) 13 Page - Integrated Device Technology |
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IDT77105 Datasheet(HTML) 13 Page - Integrated Device Technology |
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13 / 24 page  13 of 24 September 11, 2000 IDT77105 1. Assert TxFull, via register 0x02, Bit 7. This stops the 77105 from receiving more data, and prevents the complete assembly of a cell for transmission. 2. Enter desired loopback mode. 3. De-assert TxFull using 0x02, Bit 7. The previously 'interrupted' cell will continue to be assembled in the transmit FIFO; on completion, it will be transmitted, as selected via the loopback mode. If this partial cell should be discarded, assertion of TxSOC will clear this 'short' cell from the internal FIFO, and normal oper- ation will resume. Entering Loopback (Cell Mode) Under UTOPIA specification, cell transfer is initiated via the TxCLAV control, which indicates that the transmission device can receive an entire 53 byte cell for transmission. Therefore, a complete cell will auto- matically be received and transmitted by the 77105, even after TxCLAV assertion is inhibited: 1. De-assert TxCLAV, using 0x02, Bit 7. As described above, under normal UTOPIA operation it is assumed that the remainder of the cell will continue to be shipped to the 77105. 2. After waiting for complete cell to be transmitted, enable desired loopback mode. If loopback is entered prior to complete cell receipt, the cell will be looped back. 3. Re-assert TxCLAV using 0x02, Bit 7. Exiting Loopback (Byte and Cell Modes) The same conditions and concerns exist for exiting loopback, as for entering these modes. Therefore, follow the above instructions, except replace step #2 with 'disable loopback mode'. 2. Counters 2. Counters 2. Counters 2. Counters Several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions. It is anticipated that these counters will be polled from time-to-time (user selectable) to evaluate performance. ! Symbol Error Counter – 8 bit counter – counts all undefined 5 bit symbols in received data stream ! TxCell Counter – 16 bit – counts all transmitted cells ! RxCell Counter – 16 bit counter – counts all received cells ! Receive HEC Error Counter – 5 bit counter – counts all received HEC errors Figure 9 Normal Mode Figure 10 PHY Loopback Figure 11 Line Loopback 25 Mbps TC PMD Line Interface Upstream System 3445 drw 12 IDT77105 Upstream System 25 Mbps TC PMD Line Interface 3445 drw 13 IDT77105 Upstream System 25 Mbps TC PMD Line Interface 3445 drw 14 IDT77105 |
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