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September 11, 2000

IDT77105

Operation and Timing

Received-cell transfer from the PHY is controlled externally and is

synchronized to RxClk. Since data transfer is dependent upon an

external system, a 2-cell FIFO is provided to buffer the receive data

path. As with the transmit path, the receive data and controls are

sampled on the rising edge of RxClk. The data is transferred from PHY

to the external system by Octet (byte-Level Handshake or Cell-Level

Handshake. Octet (byte)-Level handshake operates as follows:

!

The PHY indicates it can transfer data into external system by

deasserting RxEmpty.

!

The RxEnb is asserted by the external system, data is clocked

on the rising edge of RxClk from PHY into external system.

Cell-Level handshake operates as follows:

!

The PHY indicates it can transfer an entire 53-byte cell into

external system by asserting RxClav.

!

The RxEnb is asserted by the external system, data is clocked

on the rising edge of RxClk from PHY into external system. Note

that for both Octet (byte)-Level Handshake and Cell-Level

Handshake modes, once the PHY indicates data transfer by

deasserting RxEmpty/asserting RxClav, the PHY has the

capability to transfer the entire 53-byte cell out unless the

RxEnb is deasserted by the external system.

Control and Status Interface

Control and Status Interface

Control and Status Interface

Control and Status Interface

The Control and Status Interface provides the data and control pins

needed to set and reset registers within the IDT77105. Registers are

used to set desired operating characteristics and functions, and to

communicate status to external systems.

The Control and Status Interface is implemented using a multiplexed

address and data bus (AD[7:0]) where the register address is latched via

the use of an Address Latch Enable.

Utility Bus

Utility Bus

Utility Bus

Utility Bus

The Utility Bus is a byte-wide interface that provides access to the

registers within the IDT77105. These registers are used to select

desired operating characteristics and functions, and to communicate

status to external systems.

The Utility Bus is implemented using a multiplexed address and data

bus (AD[7:0]) where the register address is latched via the Address

Latch Enable (ALE) signal.

The Utility Bus interface is comprised of the following pins:

AD[7:0]

ALE

CS

RDB

WRB

Read Operation

Read Operation

Read Operation

Read Operation

Refer to the Utility Bus waveforms on Figures 19 - 20. A register read

is performed as follows:

1. Initial condition:

– RDB, WRB, CS not asserted (logic 1)

– ALE not asserted (logic 0)

2. Set up register address:

– place desired register address on AD[7:0]

– set ALE to logic 1;

– latch this address by setting ALE to logic 0.

3. Read register data:

– Remove register address data from AD[7:0]

– assert CS by setting to logic 0;

– assert RDB by setting to logic 0

– wait minimum pulse width time (see AC specifications)

Write Operation

Write Operation

Write Operation

Write Operation

A register write is performed as described below:

1. Initial condition:

– RDB, WRB, CS not asserted (logic 1)

– ALE not asserted (logic 0)

2. Set up register address:

– place desired register address on AD[7:0]

– set ALE to logic 1;

– latch this address by setting ALE to logic 0.

3. Write data:

– place data on AD[7:0]

– assert CS by setting to logic 0;

– assert WRB (logic 0) for minimum time (according to timing

specification); reset WRB to logic 1 to complete register write

cycle.

Interrupt Operations

Interrupt Operations

Interrupt Operations

Interrupt Operations

The IDT77105 provides a variety of selectable interrupt and signal-

ling conditions which are useful both during ‘normal’ operation, and as

diagnostic aids. Refer to the Status and Control Register List starting on

Page 18.

Overall interrupt control is provided via register 0x00, bit 0. When this

bit is cleared (set to 0), interrupt signalling is prevented. Additional inter-

rupt signal control is provided by register 0x00, bit 5. When this bit is set

(=1), receive cell errors will be flagged via interrupt signalling and all

other interrupt conditions are masked. These errors include:

– Bad receive HEC

– Short (fewer than 53 bytes) cells

– Received cell symbol error

Normal interrupt operations are performed by setting register 0x00

bit-0 = 1, and bit-5 = 0. INT (pin 53) will go to a low state when an inter-

rupt condition is detected. The external system should then interrogate

the 77105 to determine which one (or more) conditions caused this flag,

and reset the interrupt for further occurrences. This is accomplished by

reading register 0x01. Decoding the bits in this byte will tell which error

condition caused the interrupt. Reading register 0x01 also:

– clears all interrupt status bits

– resets INT