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IDT77105 Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT77105 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 24 page  7 of 24 September 11, 2000 IDT77105 The 'Scrambler' takes each nibble of data and exclusive-ORs them against the 4 high order bits (X(t), X(t-1), X(t-2), X(t-3)) of a 10 bit pseudo-random nibble generator (PRNG). Its function is to provide the appropriate frequency distribution for the signal across the line. The PRNG is clocked every time a nibble is processed, regardless of whether the processed nibble is part of a data or command byte. Note however that only data nibbles are scrambled. The entire command byte (X _C) is NOT scrambled before it's encoded (see diagram for illustra- tion). The PRNG is based upon the following polynomial: X10 + X7 + 1 With this polynomial, the four output data bits (D3, D2, D1, D0) will be generated from the following equations: D3 = d3 xor X(t-3) D2 = d2 xor X(t-2) D1 = d1 xor X(t-1) D0 = d0 xor X(t) The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and X(t+1). A scrambler lock between the transmitter and receiver occurs each time an X_X command is sent. An X_X command is initiated only at the beginning of a cell transfer after the PRNG has cycled through all of its states (210 - 1 = 1023 states). The first valid ATM data cell transmitted after power on will also be accompanied with an X_X command byte. Each time an X_X command byte is sent, the first nibble after the last escape (X) nibble is XOR'd with 1111b (PRNG = 3FFx). Because a timing marker command (X_8) may occur at any time, the possibility of a reset PRNG start-of-cell command and a timing marker command occurring consecutively does exist (e.g. X_X_X_8). In this case, the detection of the last two consecutive escape (X) nibbles will cause the PRNG to reset to its initial 3FFx state. Therefore, the PRNG is clocked only after the first nibble of the second consecutive escape pair. Once the data nibbles have been scrambled using the PRNG, the nibbles are further encoded using a 4b/5b process. The 4b/5b scheme ensures that an appropriate number of signal transitions occur on the line. A total of 17 5-bit symbols are used to represent the 16 4-bit data nibbles and the one escape (X) nibble. The table below lists the 4-bit data with their corresponding 5-bit symbols: Data 0000 0100 1000 1100 Symbol 10101 00111 10010 10111 Symbol 01001 01101 11001 11101 Data 0001 0101 1001 1101 Symbol 01010 01110 11010 11110 Data 0010 0110 1010 1110 Data 0011 0111 1011 1111 ESC(X) = 00010 3445 drw 03a Symbol 01011 01111 11011 11111 . . This encode/decode implementation has several very desirable prop- erties. Among them is the fact that the output symbol bits can be repre- sented by a set of relatively simple logic equations. The other main advantage is that it contains transmission properties that are desirable, which include: ! Transition averages over 3 per 5 signal elements; ! Encode/Decode is not affected by the incorporation of the scrambler; ! Run length is limited to <= 5; ! Disparity never exceeds +/- 1. On the receiver, the decoder determines from the received symbols whether a timing marker command (X_8) or a start-of-cell command was sent (X_X or X_4). If a start-of-cell command is detected, the next 53 bytes received are decoded and forwarded to the descrambler. (See Receive Block Diagram, Figure 2). The output of the 4b/5b encoder provides serial data to the NRZI encoder. The NRZI code transitions the wire voltage each time a '1' bit is sent. This, together with the previous encoding schemes guarantees that long run lengths of either '0' or '1's are prevented. Each symbol is shifted out with its most significant bit sent first. When it has no cells to transmit, the 77105 keeps the line active by continuing to transmit valid symbols. It does not, however, transmit another start-of-cell command until it has another cell for transmission. Transmit HEC Byte Calculation/Insertion Byte #5 of each ATM cell, the HEC (Header Error Control) is calcu- lated automatically across the first 4 bytes of the cell header, depending upon the setting of bit 5 of register 0x03. This byte is then either inserted as a replacement of the fifth byte transferred to the PHY by the external system, or the cell is transmitted as received. A second operating mode provides for insertion of "Bad" HEC codes which may aid in communica- tion diagnostics. Receiver Description On the receiving end, the inverse occurs. The data is NRZI decoded before each symbol is reassembled. The symbols are then sent to the 5b/4b decoder, followed by the Command Byte Interpreter, De-Scram- bler, and finally the UTOPIA interface to the outside world. Note that although the IDT77105 can detect symbol and HEC errors, it does not attempt to correct them. ATM Cell Format Bit 7 Bit 0 Bit7 Bit0 Header Byte 1 Header Byte 2 Header Byte 3 Header Byte 4 UDF Payload Byte 1 • •• Payload Byte 48 3445 drw 03b UDF = User Defined Field (or HEC) |
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