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IDT77105 Datasheet(PDF) 19 Page - Integrated Device Technology

Part # IDT77105
Description  PHY (TC-PMD) for 25.6 Mbps ATM Networks
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT77105 Datasheet(HTML) 19 Page - Integrated Device Technology

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September 11, 2000
IDT77105
UTOPIA Bus Timing Parameters
UTOPIA Bus Timing Parameters
UTOPIA Bus Timing Parameters
UTOPIA Bus Timing Parameters
Figure 17 UTOPIA Receive
TxOSC and Reset Timing
TxOSC and Reset Timing
TxOSC and Reset Timing
TxOSC and Reset Timing
Symbol
Parameter
Min.
Max.
Unit
t1
RxEnb set up time to RxCLK
10
ns
t2
RxEnb hold time from RxCLK
2
ns
t3
tPD from RxCLK to RxSOC, RxData, and RxRef
3
10
ns
t4
RxEmpty delay from RxCLK
1
20
ns
t5
TxData[7:0], TxParity setup time to TxCLK
10
ns
t6
TxData[7:0], TxParity hold time from TxCLK
2
ns
t7
TxSOC, TxEnb setup time to TxCLK
10
ns
t8
TxSOC, TxEnb hold time from TxCLK
2
ns
t9
TxFull delay from TxCLK
1
20
ns
t10
TxRef pulse width
TxCLK Period +5ns
ns
t11
RxCLK period
30
400
ns
t12
RxCLK duty cycle (T of t11)
40
60
ns
t13
TxCLK period
30
400
ns
t14
TxCLK duty cycle (% of t13)
40
60
ns
t15
RxCLK to RxData [7:0], RxParity, and RxSOC low impedance
2
12
ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
Tcyc
TxOSC frequency (25.6 Mbps)
31.5
32
32.5
MHz
Tch
TxOSC high duty cycle (% of Tcyc)
40
50
50
%
Tcl
TxOSC low duty cycle (% of Tcyc))
40
50
50
%
Trpw1
1. Trpw must meet both minimum limits.
Minimum Resetpulse width
2* TxCLK period
2* RxCLK period
RxCLK
RxSOC
RxEmpty/RxClav
RxEnb
RxData [7:0],
RxParity
3445 drw 20
Octet 1
Octet 2
Octet 49
Oct
t1
t4
t2
RxRef
t15
t3
t11
t12
Hi-Z
Hi-Z
Octet 0


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