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ATF22V10CQ-15JC Datasheet(PDF) 1 Page - ATMEL Corporation |
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ATF22V10CQ-15JC Datasheet(HTML) 1 Page - ATMEL Corporation |
1 / 18 page 1 Features • Industry-standard Architecture – Low-cost, Easy-to-use Software Tools • High-speed, Electrically Erasable Programmable Logic Devices – 5 ns Maximum Pin-to-pin Delay • CMOS- and TTL-compatible Inputs and Outputs – Latch Feature Holds Inputs to Previous Logic States • Pin-controlled Standby Power (10 µA Typical) • Advanced Flash Technology – Reprogrammable – 100% Tested • High-reliability CMOS Process – 20-year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latch-up Immunity • Dual Inline and Surface Mount Packages in Standard Pinouts • PCI-compliant • True Input Transition Detection “Z” and “QZ” Version High- performance EE PLD ATF22V10C ATF22V10CQ See separate datasheet for ATF22V10CZ and ATF22V10CQZ options. Rev. 0735P–PLD–01/02 TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK/IN IN IN IN/PD IN IN IN IN IN IN IN GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN Pin Configurations All Pinouts Top View Pin Name Function CLK Clock IN Logic Inputs I/O Bi-directional Buffers GND Ground VCC +5V Supply PD Power-down DIP/SOIC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK/IN IN IN IN/PD IN IN IN IN IN IN IN GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN PLCC Note: For all PLCCs (except “-5”), pins 1, 8, 15 and 22 can be left unconnected. However, if they are connected, supe- rior performance will be achieved. 5 6 7 8 9 10 11 25 24 23 22 21 20 19 IN/PD IN IN GND* IN IN IN I/O I/O I/O GND* I/O I/O I/O |
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