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AD7715 Datasheet(PDF) 24 Page - Analog Devices |
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AD7715 Datasheet(HTML) 24 Page - Analog Devices |
24 / 41 page ![]() Data Sheet AD7715 Rev. E | Page 23 of 40 ANALOG FILTERING The digital filter does not provide any rejection at integer mul- tiples of the modulator sample frequency, as outlined earlier. However, due to the high oversampling ratio of AD7715, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. This means that the analog filtering requirements in front of the AD7715 are considerably reduced vs. a conventional converter with no on-chip filtering. In addition, because the part’s common-mode rejection performance of 95 dB extends out to several kilohertz, common-mode noise in this frequency range is substantially reduced. Depending on the application, however, it may be necessary to provide attenuation in front of the AD7715 to eliminate unwanted frequencies from these bands which the digital filter will pass. It may also be necessary in some applications to provide analog filtering in front of the AD7715 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator. If passive components are placed in front of the AD7715, in unbuffered mode, take care to ensure that the source impedance is low enough so as not to introduce gain errors in the system. This significantly limits the amount of passive antialiasing filtering which can be provided in front of the AD7715 when it is used in unbuffered mode. However, when the part is used in buffered mode, large source impedances simply result in a small dc offset error (a 10 kΩ source resistance causes an offset error of less than 10 µV). Therefore, if the system requires any significant source impedances to provide passive analog filtering in front of the AD7715, it is recommended that the part be operated in buffered mode. CALIBRATION The AD7715 provides a number of calibration options that can be programmed via the MD1 and MD0 bits of the setup register. The different calibration options are outlined in the setup register and calibration sequences sections. A calibration cycle may be initiated at any time by writing to the MD1 and MD0 bits of the setup register. Calibration on the AD7715 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch or bipolar/unipolar input range. The AD7715 offers self-calibration and system-calibration facilities. For full calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. These are zero-scale and full-scale points. These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. As a result, the accuracy of the calibration can only be as good as the noise level that it provides in normal mode. The result of the zero-scale calibration conversion is stored in the zero-scale calibration register while the result of the full-scale calibration conversion is stored in the full-scale calibration register. With these readings, the on-chip microcontroller can calculate the offset and the gain slope for the input to output transfer function of the converter. Internally, the part works with a resolution of 33 bits to determine its conversion result of 16 bits. Self-Calibration A self-calibration is initiated on the AD7715 by writing the appropriate values (0, 1) to the MD1 and MD0 bits of the setup register. In the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with the inputs of the differential pair internally shorted on the part (that is, AIN(+) = AIN(−) = internal bias voltage). The PGA is set for the selected gain (as per G1 and G0 bits in the communications register) for this zero-scale calibration conversion. The full-scale calibration conversion is performed at the selected gain on an internally generated voltage of VREF/selected gain. The duration time for the calibration is 6 × 1/output rate. This is made up of 3 × 1/output rate for the zero-scale calibration and 3 × 1/output rate for the full-scale calibration. At this time, the MD1 and MD0 bits in the setup register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 9 × 1/output rate. This is made up of 3 × 1/output rate for the zero-scale calibration, 3 × 1/output rate for the full-scale calibration, 3 × 1/output rate for a conversion on the analog input and some overhead to set up the coefficients correctly. If DRDY is low before (or goes low during) the calibration command write to the setup register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. For bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. In this case, the two points are exactly the same as above, but because the part is configured for bipolar operation, the shorted inputs point is actually midscale of the transfer function. |
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