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TM893CBK32 Datasheet(PDF) 7 Page - Texas Instruments |
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TM893CBK32 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 9 page ![]() TM893CBK32, TM893CBK32S 8388608 BY 32-BIT DYNAMIC RAM MODULE SMMS652A – FEBRUARY 1995 – REVISED JUNE 1995 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (concluded) ’893CBK32-60 ’893CBK32-70 ’893CBK32-80 UNIT MIN MAX MIN MAX MIN MAX UNIT tCAH Hold time, column address after CAS low 10 15 15 ns tDH Hold time, data after CAS and W low 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tWCH Hold time, W low after CAS low 10 15 15 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tCHR Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns tCRP Delay time, CAS high to RAS low 5 5 5 ns tCSH Delay time, RAS low to CAS high 60 70 80 ns tCSR Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns tRAD Delay time, RAS low to column address (see Note 10) 15 30 15 35 15 40 ns tRAL Delay time, column address to RAS high 30 35 40 ns tCAL Delay time, column address to CAS high 30 35 40 ns tRCD Delay time, RAS low to CAS low (see Note 10) 20 45 20 52 20 60 ns tRPC Delay time, RAS high to CAS low (CBR refresh only) 0 0 0 ns tRSH Delay time, CAS low to RAS high 15 18 20 ns tREF Refresh time interval 32 32 32 ms tT Transition time 3 30 3 30 3 30 ns NOTES: 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time. |
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