AD7707

Rev. B | Page 20 of 52

Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01

The setup register is an eight-bit register from which data can either be read or to which data can be written. Table 18 outlines the bit

designations for the setup register.

Table 18. Setup Register

MD1 (0)

MD0 (0)

G2 (0)

G1 (0)

G0 (0)

B/U (0)

BUF (0)

FSYNC (1)

Table 19.

Bit

Description

MD1, MD0

Operating mode selection bits.

G2 to G0

Gain selection bits. These bits select the gain setting for the on-chip PGA, as outlined in Table 21.

B/U

Bipolar/unipolar operation. A 0 in this bit selects Bipolar operation. A 1 in this bit selects unipolar operation.

BUF

Buffer control. With this bit at 0, the on-chip buffer on the analog input is shorted out. With the buffer shorted out, the

allowing the input to handle higher source impedances.

FSYNC

Filter synchronization. When this bit is high, the nodes of the digital filter, the filter control logic, and the calibration

control logic are held in a reset state, and the analog modulator is held in its reset state. When this bit goes low, the

modulator and filter start to process data and a valid word is available in 3 × 1/(output update rate), that is, the settling

time of the filter. This FSYNC bit does not affect the digital interface and does not reset the DRDY output if it is low.

Table 20. Operating Modes

MD1

MD0

Operating Mode

0

0

Normal mode: this is the normal mode of operation of the device whereby the device is performing normal conversions.

0

1

Self-calibration: this activates self-calibration on the channel selected by CH1 and CH0 of the communications register.

This is a one-step calibration sequence and, when complete, the part returns to normal mode with MD1 and MD0

returning to 0, 0. The DRDY output or bit goes high when calibration is initiated and returns low when this self-

calibration is complete and a new valid word is available in the data register. The zero-scale calibration is performed at

the selected gain on internally shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on

1

0

Zero-scale (ZS) system calibration: this activates zero-scale system calibration on the channel selected by CH1 and CH0

of the communications register. Calibration is performed at the selected gain on the input voltage provided at the

analog input during this calibration sequence. This input voltage should remain stable for the duration of the

calibration. The DRDY output or bit goes high when calibration is initiated and returns low when this zero-scale

calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part

returns to ormal

ode with MD1 and MD0 returning to 0, 0.

1

1

Full-scale (FS) system calibration: this activates full-scale system calibration on the selected input channel. Calibration is

performed at the selected gain on the input voltage provided at the analog input during this calibration sequence. This

input voltage should remain stable for the duration of the calibration. The DRDY output or bit goes high when

calibration is initiated and returns low when this full-scale calibration is complete and a new valid word is available in

the data register. At the end of the calibration, the part returns to normal mode with MD1 and MD0 returning to 0, 0.

Table 21. Gain Selection

G2

G1

G0

Gain Setting

0

0

0

1

0

0

1

2

0

1

0

4

0

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128