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AD7707 Datasheet(PDF) 23 Page - Analog Devices |
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AD7707 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 53 page  AD7707 Rev. B | Page 22 of 52 Table 24. Output Update Rates CLK1 FS2 FS1 FS0 Output Update Rate −3 dB Filter Cutoff 0 0 0 0 20 Hz 5.24 Hz 0 0 0 1 25 Hz 6.55 Hz 0 0 1 0 100 Hz 26.2 Hz 0 0 1 1 200 Hz 52.4 Hz 1 0 0 0 50 Hz 13.1 Hz 1 0 0 1 60 Hz 15.7 Hz 1 0 1 0 250 Hz 65.5 Hz 1 0 1 1 500 Hz 131 Hz 0 1 0 0 4.054 Hz 1.06 Hz 0 1 0 1 4.23 Hz 1.11 Hz 0 1 1 0 4.84 Hz 1.27 Hz 0 1 1 1 4.96 Hz 1.3 Hz 1 1 0 0 10 Hz 2.62 Hz 1 1 0 1 10.34 Hz 2.71 Hz 1 1 1 0 11.90 Hz 3.13 Hz 1 1 1 1 12.2 Hz 3.2 Hz 1 Assumes correct clock frequency on the MCLK IN pin with the CLKDIV bit set appropriately. Data Register (RS2, RS1, RS0 = 0, 1, 1) The data register on the part is a 16-bit read-only register that contains the most up-to-date conversion result from the AD7707. If the communications register sets up the part for a write operation to this register, a write operation must actually take place to return the part to where it is expecting a write operation to the communications register. However, the 16 bits of data written to the part are ignored by the AD7707. Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset Status: 0x00 The part contains a est egister that is used when testing the device. The user is advised not to change the status of any of the bits in this register from the default (power-on or RESET) status of all 0s because the part will be placed in one of its test modes and will not operate correctly. Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 The AD7707 contains independent sets of zero-scale registers, one for each of the input channels. Each of these registers is a 24-bit read/write register; 24 bits of data must be written; otherwise, no data is transferred to the register. This register is used in conjunction with its associated full-scale register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table 17. Although the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking the FSYNC bit in the setup register high before the calibration register operation and taking it low after the operation is complete. Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1); Power-On/Reset Status: 0x5761AB The AD7707 contains independent sets of full-scale registers, one for each of the input channels. Each of these registers is a 24-bit read/write register; 24 bits of data must be written; otherwise, no data is transferred to the register. This register is used in conjunction with its associated zero-scale register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table 17. Although the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the register coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or write operation) the first output data read from the part may contain incorrect data. In addition, a write to the calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking FSYNC bit in the setup register high before the calibration register operation and taking it low after the operation is complete. |
Similar Part No. - AD7707_17 |
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Similar Description - AD7707_17 |
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