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AD7707 Datasheet(PDF) 9 Page - Analog Devices |
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AD7707 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 53 page  AD7707 Rev. B | Page 8 of 52 TIMING CHARACTERISTICS AVDD = DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; input logic = 0, Logic 1 = DVDD, unless otherwise noted. Table 4. Parameter1, 2 Limit at TMIN, TMAX (B Version) Unit Conditions/Comments fCLKIN3, 4 400 kHz min Master clock frequency: crystal oscillator or externally supplied for specified performance 5 MHz max tCLKIN LO 0.4 × tCLKIN ns min Master clock input low time, tCLKIN = 1/fCLKIN tCLKIN HI 0.4 × tCLKIN ns min Master clock input high time t1 500 × tCLKIN ns nom DRDY high time t2 100 ns min RESET pulse width Read Operation t3 0 ns min DRDY to CS setup time t4 120 ns min CS falling edge to SCLK rising edge setup time t55 0 ns min SCLK falling edge to data valid delay 80 ns max DVDD = 5 V 100 ns max DVDD = 3.0 V t6 100 ns min SCLK high pulse width t7 100 ns min SCLK low pulse width t8 0 ns min CS rising edge to SCLK rising edge hold time t96 10 ns min Bus relinquish time after SCLK rising edge 60 ns max DVDD = 5 V 100 ns max DVDD = 3.0 V t10 100 ns max SCLK falling edge to DRDY high7 Write Operation t11 120 ns min CS falling edge to SCLK rising edge setup time t12 30 ns min Data valid to SCLK rising edge setup time t13 20 ns min Data valid to SCLK rising edge hold time t14 100 ns min SCLK high pulse width t15 100 ns min SCLK low pulse width t16 0 ns min CS rising edge to SCLK rising edge hold time 1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 20 and Figure 21. 3 fCLKIN duty cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7707 is not in standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 The AD7707 is production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz. 5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care should be taken that subsequent reads do not occur close to the next output update. TO OUTPUT PIN 50pF ISINK (800µA AT VDD = 5V 100µA AT VDD = 3V) 1.6V ISOURCE (200µA AT VDD = 5V 100µA AT VDD = 3V) Figure 2. Load Circuit for Access Time and Bus Relinquish Time |
Similar Part No. - AD7707_17 |
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Similar Description - AD7707_17 |
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