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AD7707 Datasheet(PDF) 32 Page - Analog Devices |
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AD7707 Datasheet(HTML) 32 Page - Analog Devices |
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32 / 53 page  AD7707 Rev. B | Page 31 of 52 MD0 bits in the setup register return to 0, 0. This gives the earliest indication that the calibration sequence is complete. The DRDY line goes high when calibration is initiated and does not return low until there is a valid new word in the data register. The duration time from the calibration command being issued to DRDY going low is 4 × 1/output rate as the part performs a normal conversion on the analog input voltage before DRDY goes low. If DRDY is low before (or goes low during) the calibration command write to the setup register, it may take up to one modulator cycle (MCLK IN/128) before DRDY goes high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit is written to the setup register in the calibration command. In the unipolar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale (zero differential voltage) and positive full scale. The fact that the system calibration is a two-step calibration offers another feature. After the sequence of a full system calibration has been completed, additional offset or gain calibrations can be performed by themselves to adjust the system zero reference point or the system gain. Calibrating one of the parameters, either system offset or system gain, does not affect the other parameter. System calibration can also be used to remove any errors from source impedances on the analog input when the part is used in unbuffered mode. A simple R, C antialiasing filter on the front end may introduce a gain error on the analog input voltage, but the system calibration can be used to remove this error. SPAN AND OFFSET LIMITS ON THE LOW LEVEL INPUT CHANNELS, AIN1 AND AIN2 Whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. The overriding requirement in determining the amount of offset and gain that can be accommodated by the part is the require- ment that the positive full-scale calibration limit is <1.05 × VREF/gain. This allows the input range to go 5% above the nominal range. The built-in headroom in the AD7707’s analog modulator ensures that the part will still operate correctly with a positive full-scale voltage that is 5% beyond the nominal. The input span in both the unipolar and bipolar modes has a minimum value of 0.8 × VREF/gain and a maximum value of 2.1 × VREF/gain. However, the span (which is the difference between the bottom of the AD7707’s input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage. The amount of offset that can be accommo- dated depends on whether the unipolar or bipolar mode is being used. Once again, the offset has to take into account the limitation on the positive full-scale voltage. In unipolar mode, there is considerable flexibility in handling negative offsets. In both unipolar and bipolar modes, the range of positive offsets that can be handled by the part depends on the selected span. Therefore, in determining the limits for system zero-scale and full-scale calibrations, the user must ensure that the offset range plus the span range does exceed 1.05 × VREF/gain. This is best illustrated with the following examples. If the part is used in unipolar mode with a required span of 0.8 × VREF/gain, the offset range the system calibration can handle is from −1.05 × VREF/gain to +0.25 × VREF/gain. If the part is used in unipolar mode with a required span of VREF/gain, the offset range the system calibration can handle is from −1.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the part is used in unipolar mode and required to remove an offset of 0.2 × VREF/gain, the span range the system calibration can handle is 0.85 × VREF/gain. AD7707 LOW LEVEL INPUT CHANNEL INPUT RANGE (0.8 × VREF/GAIN TO 2.1 × VREF/GAIN) UPPER LIMIT ON AD7707 INPUT VOLTAGE NOMINAL ZERO- SCALE POINT OFFSET CALIBRATIONS MOVE INPUT RANGE UP OR DOWN LOWER LIMIT ON AD7707 INPUT VOLTAGE –1.05 × VREF/GAIN 0V DIFFERENTIAL GAIN CALIBRATIONS EXPAND OR CONTRACT THE AD7707 INPUT RANGE 1.05 × VREF/GAIN Figure 17. Span and Offset Limits for Low Level Input Channels, AIN1 and AIN2 If the part is used in bipolar mode with a required span of ±0.4 × VREF/gain, the offset range the system calibration can handle is from –0.65 × VREF/gain to +0.65 × VREF/gain. If the part is used in bipolar mode with a required span of ±VREF/gain, then the offset range that the system calibration can handle is from −0.05 × VREF/gain to +0.05 × VREF/gain. Similarly, if the part is used in bipolar mode and required to remove an offset of ±0.2 × VREF/gain, the span range the system calibration can handle is ±0.85 × VREF/gain. Figure 17 shows a graphical representation of the span and offset limits for the low level input channels. SPAN AND OFFSET LIMITS ON THE HIGH LEVEL INPUT CHANNEL AIN3 The exact same reasoning for low level input channels can applied to the high level input channel. When using the high level channel, the attenuator provides an attenuation factor of 8. All span and offset limits should be multiplied by a factor of 8. Therefore, the range of input span in both the unipolar and bipolar modes has a minimum value of 6.4 × VREF/gain and a maximum value of 16.8 × VREF/gain. The offset range plus the span range cannot exceed 8.4 × VREF/gain. |
Similar Part No. - AD7707_17 |
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Similar Description - AD7707_17 |
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