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MX98715AEC-C Datasheet (PDF) - Macronix International

MX98715AEC-C Datasheet PDF - Macronix International
Part # MX98715AEC-C
Download  MX98715AEC-C Download

File Size   201.87 Kbytes
Page   39 Pages
Manufacturer  MCNIX [Macronix International]
Direct Link  http://www.macronix.com
Logo MCNIX - Macronix International
Description SINGLE CHIP FAST ETHERNET NIC CONTROLLER - CRYSTAL VERSION

MX98715AEC-C Datasheet (PDF)

Go To PDF Page Download Datasheet
MX98715AEC-C Datasheet PDF - Macronix International

Part # MX98715AEC-C
Download  MX98715AEC-C Click to download

File Size   201.87 Kbytes
Page   39 Pages
Manufacturer  MCNIX [Macronix International]
Direct Link  http://www.macronix.com
Logo MCNIX - Macronix International
Description SINGLE CHIP FAST ETHERNET NIC CONTROLLER - CRYSTAL VERSION

MX98715AEC-C Datasheet (HTML) - Macronix International

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MX98715AEC-C Product details

GENERAL DESCRIPTIONS
The MX98715AEC-C controller is an IEEE802.3u compliant single chip 32-bit full duplex, 10/100Mbps highly integrated Fast Ethernet combo solution, designed to address high performance local area networking (LAN) system application requirements.

FEATURES
• A single chip solution integrates 100/10 Base-T fast Ethernet MAC, PHY and PMD.
• Microsoft PC97, 98, 99 and Novell 4.11/5.0 certified.
• Support DMI 2.0 management.
• Support Intel PXE remote boot device.
• Fully comply to IEEE 802.3u specification.
• Operates over 100 meters of STP and category 5 UTP cable.
• Fully comply to PCI spec. 2.1 with clock frequency up to 33MHz.
• Fully comply to Advanced Configuration and Power Interface (ACPI) Rev 1.1
• Fully comply to PCI Bus Power Management Interface spec. Rev 1.1
• Support full and half duplex operations in both 100 Base-TX and 10 Base-T mode.
• Supports 3 kinds of wake up events defined in Network Device Class Power Management Spec 1.0. Including:
    - Magic PacketTM
    - Link Change(link-on)
    - Wake Up Frame
• Supports IEEE802.3x Frame Based Flow Control scheme in full duplex mode.
• Supports early interrupt on both transmit and receive operations.
• 100/10 Base-T NWAY auto negotiation function
• Large on-chip FIFOs for both transmit and receive operations without external local memory
• Bus master architecture with linked host buffers delivers the most optimized performance
• 32-bit bus master DMA channel provides ultra low CPU utilization, best fit in server and windows application.
• Proprietary Adaptive Network Throughput Control (ANTC) technology to optimize data integrity and throughput
• Support up to 64K bytes boot ROM interface
• Three levels of loopback diagnositic capability
• Support a variety of flexible address filtering modes with 16 CAM address and 128 bits hash
• MicroWire interface to EEPROM for customers IDs and configuration data
• Single +5V power supply, CMOS technology, 128-pin PQFP package/LQPF package




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