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ISPLSI2128VE-100LTN100 Datasheet (PDF) - Lattice Semiconductor

ISPLSI2128VE-100LTN100 Datasheet PDF - Lattice Semiconductor
Part No. ISPLSI2128VE-100LTN100
Download  ISPLSI2128VE-100LTN100 Click to view

File Size   206.11 Kbytes
Page   20 Pages
Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor
Description 3.3V In-System Programmable SuperFAST??High Density PLD

ISPLSI2128VE-100LTN100 Datasheet (PDF)

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ISPLSI2128VE-100LTN100 Datasheet PDF - Lattice Semiconductor

Part No. ISPLSI2128VE-100LTN100
Download  ISPLSI2128VE-100LTN100 Click to view

File Size   206.11 Kbytes
Page   20 Pages
Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor
Description 3.3V In-System Programmable SuperFAST??High Density PLD

ISPLSI2128VE-100LTN100 Datasheet (HTML) - Lattice Semiconductor

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ISPLSI2128VE-100LTN100 Product details

Description
The ispLSI 2128VE is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions.

Features
• SuperFAST HIGH DENSITY IN-SYSTEM
   PROGRAMMABLE LOGIC
   — 6000 PLD Gates
   — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
   — 128 Registers
   — High Speed Global Interconnect
   — Wide Input Gating for Fast Counters, State
      Machines, Address Decoders, etc.
   — Small Logic Block Size for Random Logic
   — 100% Functional, JEDEC and Pinout Compatible
      with ispLSI 2128V Devices
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE
   — Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   — fmax = 250MHz Maximum Operating Frequency
   — tpd = 4.0ns Propagation Delay
   — Electrically Erasable and Reprogrammable
   — Non-Volatile
   — 100% Tested at Time of Manufacture
   — Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
   — 3.3V In-System Programmability (ISP™) Using
      Boundary Scan Test Access Port (TAP)
   — Open-Drain Output Option for Flexible Bus Interface
      Capability, Allowing Easy Implementation of Wired
      OR Bus Arbitration Logic
   — Increased Manufacturing Yields, Reduced Time-to
      Market and Improved Product Quality
   — Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
   PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
   — Enhanced Pin Locking Capability
   — Three Dedicated Clock Input Pins
   — Synchronous and Asynchronous Clocks
   — Programmable Output Slew Rate Control
   — Flexible Pin Placement
   — Optimized Global Routing Pool Provides Global
      Interconnectivity
• LEAD-FREE PACKAGE OPTIONS



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