Overview This chapter provides an overview of the MCF5272 microprocessor features, including the major functional components. MCF5272 Key Features A block diagram of the MCF5272 is shown in Figure 1-1. The main features are as follows: • Static Version 2 ColdFire variable-length RISC processor — 32-bit address and data path on-chip — 66-MHz processor core and bus frequency — Sixteen general-purpose 32-bit data and address registers — Multiply-accumulate unit (MAC) for DSP and fast multiply operations • On-chip memories — 4-Kbyte SRAM on CPU internal bus — 16-Kbyte ROM on CPU internal bus — 1-Kbyte instruction cache • Power management — Fully-static operation with processor sleep and whole-chip stop modes — Very rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used — Software-controlled disable of external clock input for virtually zero power consumption (low-power stop mode) • Two universal asynchronous/synchronous receiver transmitters (UARTs) — Full-duplex operation — Based on MC68681 dual-UART (DUART) programming model — Flexible baud rate generator — Modem control signals available (CTS and RTS) — Processor interrupt and wakeup capability — Enhanced Tx, Rx FIFOs, 24 bytes each • Ethernet Module — 10 baseT capability, half or full duplex — 100 baseT capability, half duplex and limited throughput full duplex (MCF5272) — On-chip transmit and receive FIFOs — Off-chip flexible buffer descriptor rings — Media-independent interface (MII) • Universal serial bus (USB) module — 12 Mbps (full speed) — Fully compatible with USB 1.1 specifications — Eight endpoints (control, bulk, interrupt Rx, isochronous) — Endpoint FIFOs — Selectable on-chip analog interface • External memory interface — External glueless 8, 16, and 32-bit SRAM and ROM interface bus — SDRAM controller supports 16–256 Mbit devices — External bus configurable for 16 or 32 bits width for SDRAM — Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator • Queued serial peripheral interface (QSPI) — Full-duplex, three-wire synchronous transfer — Up to four chip selects available — Master operation — Programmable master bit rates — Up to 16 preprogrammed transfers • Timer module — 4x16-bit general-purpose multi-mode timer – Input capture and output compare pins for timers 1 and 2 – Programmable prescaler — 15-nS resolution at 66-MHz clock frequency — Software watchdog timer — Software watchdog can generate interrupt before reset — Processor interrupt for each timer • Pulse-width modulation (PWM) unit — Three identical channels — Independent prescaler TAP point — Period/duty range variable • System integration module (SIM) — System configuration including internal and external address mapping — System protection by hardware watchdog — Versatile programmable chip-select signals with wait-state generation logic — Up to three 16-bit parallel input/output ports — Latchable interrupt inputs with programmable priority and edge triggering — Programmable interrupt vectors for on-chip peripherals • Physical layer interface controller (PLIC) — Allows connection using general circuit interface (GCI) or interchip digital link (IDL) physical layer protocols for 2B + D data — Three physical interfaces — Four time-division multiplex (TDM) ports • IEEE 1149.1 boundary-scan test access port (JTAG) for board-level testing • Operating voltage: 3.3 V ±0.3 V • Operating temperature: 0 –70°C • Operating frequency: DC to 66 MHz, from external CMOS oscillator • Compact ultra low-profile 196 ball-molded plastic ball-grid array package (PGBA)
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