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W631GG6KB-15 Datasheet (PDF) - Winbond

W631GG6KB-15 Datasheet PDF - Winbond
Part No. W631GG6KB-15
Download  W631GG6KB-15 Click to view

File Size   3610.9 Kbytes
Page   158 Pages
Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond
Description Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB-15 Datasheet (PDF)

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W631GG6KB-15 Datasheet PDF - Winbond

Part No. W631GG6KB-15
Download  W631GG6KB-15 Click to view

File Size   3610.9 Kbytes
Page   158 Pages
Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond
Description Double Data Rate architecture: two data transfers per clock cycle

W631GG6KB-15 Datasheet (HTML) - Winbond

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W631GG6KB-15 Product details

GENERAL DESCRIPTION

The W631GG6KB is a 1G bits DDR3 SDRAM, organized as 8,388,608 words x 8 banks x 16 bits. This device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various applications. W631GG6KB is sorted into the following speed grades: -11, -12, 12I, 12A, 12K -15, 15I, 15A and 15K. The -11 speed grade is compliant to the DDR3-1866 (13-13-13) specification. The -12, 12I, 12A and 12K speed grades are compliant to the DDR3-1600 (11-11-11) specification (the 12I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -15, 15I, 15A and 15K speed grades are compliant to the DDR3-1333 (9-9-9) specification (the 15I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C).



FEATURES

 Power Supply: VDD, VDDQ = 1.5V ± 0.075V

 Double Data Rate architecture: two data transfers per clock cycle

 Eight internal banks for concurrent operation

 8 bit prefetch architecture

 CAS Latency: 6, 7, 8, 9, 10, 11 and 13

 Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On The-Fly (OTF)

 Programmable read burst ordering: interleaved or nibble sequential

 Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data

 Edge-aligned with read data and center-aligned with write data

 DLL aligns DQ and DQS transitions with clock

 Differential clock inputs (CK and CK#)

 Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate)

 Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command, address and data bus efficiency

 Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)

 Auto-precharge operation for read and write bursts

 Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)

 Precharged Power Down and Active Power Down



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