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CY7C2168KV18 Datasheet (PDF) - Cypress Semiconductor

CY7C2168KV18 Datasheet PDF - Cypress Semiconductor
Part # CY7C2168KV18
Download  CY7C2168KV18 Download

File Size   879.91 Kbytes
Page   29 Pages
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor
Description 18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C2168KV18 Datasheet (PDF)

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CY7C2168KV18 Datasheet PDF - Cypress Semiconductor

Part # CY7C2168KV18
Download  CY7C2168KV18 Click to download

File Size   879.91 Kbytes
Page   29 Pages
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor
Description 18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C2168KV18 Datasheet (HTML) - Cypress Semiconductor

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CY7C2168KV18 Product details

Functional Description

The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C2168KV18), or 36-bit words (CY7C2170KV18) that burst sequentially into or out of the device.



Features

■ 18-Mbit density (1 M × 18, 512 K × 36)

■ 550-MHz clock for high bandwidth

■ Two-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing

  ❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-die termination (ODT) feature

   ❐ Supported for D[x:0], BWS[x:0], and K/K inputs

■ Synchronous internally self-timed writes

■ DDR II+ operates with 2.5 cycle read latency when DOFF is asserted HIGH

■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted LOW

■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]

   ❐ Supports both 1.5 V and 1.8 V I/O supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ CY7C2168KV18 offered in non Pb-free packages and CY7C2170KV18 offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement



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About Cypress Semiconductor


Cypress Semiconductor is an American company that specializes in the design and manufacture of high-performance digital and analog integrated circuits (ICs).
The company was founded in 1982 and is headquartered in San Jose, California, USA.
Cypress offers a wide range of products including microcontrollers, memory products, wireless connectivity solutions, and other digital and analog ICs.
The company's products are used in various applications such as consumer electronics, automotive systems, industrial systems, and more.
Cypress is known for its expertise in mixed-signal and programmable system-on-a-chip (PSoC) technology, high-quality products, and innovation in the field of embedded systems.

*This information is for general informational purposes only, we will not be liable for any loss or damage caused by the above information.




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