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MCM63P737K Datasheet (PDF) - Motorola, Inc

MCM63P737K Datasheet PDF - Motorola, Inc
Part No. MCM63P737K
Download  MCM63P737K Click to view

File Size   395.51 Kbytes
Page   20 Pages
Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc
Description 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P737K Datasheet (PDF)

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MCM63P737K Datasheet PDF - Motorola, Inc

Part No. MCM63P737K
Download  MCM63P737K Click to view

File Size   395.51 Kbytes
Page   20 Pages
Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc
Description 128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM63P737K Datasheet (HTML) - Motorola, Inc

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MCM63P737K Product details

128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM63P737K and MCM63P819K are 4M–bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache. The MCM63P737K (organized as 128K words by 36 bits) and the MCM63P819K (organized as 256K words by 18 bits) integrate input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
The MCM63P737K and MCM63P819K operate from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–5 compatible.

• MCM63P737K/MCM63P819K–166 = 3.5 ns Access/6 ns Cycle (166 MHz)
   MCM63P737K/MCM63P819K–150 = 3.8 ns Access/6.7 ns Cycle (150 MHz)
   MCM63P737K/MCM63P819K–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
• 3.3 V +10%, –5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages



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