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CY7C1315CV18-300BZXC Datasheet (PDF) - Cypress Semiconductor

CY7C1315CV18-300BZXC Datasheet PDF - Cypress Semiconductor
Part # CY7C1315CV18-300BZXC
Download  CY7C1315CV18-300BZXC Download

File Size   695.1 Kbytes
Page   31 Pages
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor
Description 18-Mbit QDR??II SRAM 4-Word Burst Architecture

CY7C1315CV18-300BZXC Datasheet (PDF)

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CY7C1315CV18-300BZXC Datasheet PDF - Cypress Semiconductor

Part # CY7C1315CV18-300BZXC
Download  CY7C1315CV18-300BZXC Click to download

File Size   695.1 Kbytes
Page   31 Pages
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor
Description 18-Mbit QDR??II SRAM 4-Word Burst Architecture

CY7C1315CV18-300BZXC Datasheet (HTML) - Cypress Semiconductor

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CY7C1315CV18-300BZXC Product details

Functional Description
The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
   
Features
■ Separate independent read and write data ports
    ❐ Supports concurrent transactions
■ 300 MHz clock for high bandwidth
■ 4-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
    (data transferred at 600 MHz) at 300 MHz
■ Two input clocks (K and K) for precise DDR timing
    ❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
    skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
    systems
■ Single multiplexed address input bus latches address inputs
    for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR™-II operates with 1.5 cycle read latency when the Delay
    Lock Loop (DLL) is enabled
■ Operates as a QDR-I device with 1 cycle read latency in DLL
    off mode
■ Available in x 8, x 9, x 18, and x 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
   




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About Cypress Semiconductor


Cypress Semiconductor is an American company that specializes in the design and manufacture of high-performance digital and analog integrated circuits (ICs).
The company was founded in 1982 and is headquartered in San Jose, California, USA.
Cypress offers a wide range of products including microcontrollers, memory products, wireless connectivity solutions, and other digital and analog ICs.
The company's products are used in various applications such as consumer electronics, automotive systems, industrial systems, and more.
Cypress is known for its expertise in mixed-signal and programmable system-on-a-chip (PSoC) technology, high-quality products, and innovation in the field of embedded systems.

*This information is for general informational purposes only, we will not be liable for any loss or damage caused by the above information.




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