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MH32S72APHB-6 Datasheet (PDF) - Mitsubishi Electric Semiconductor

MH32S72APHB-6 Datasheet PDF - Mitsubishi Electric Semiconductor
Part No. MH32S72APHB-6
Download  MH32S72APHB-6 Click to view

File Size   703.35 Kbytes
Page   55 Pages
Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Description 2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM

MH32S72APHB-6 Datasheet (PDF)

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MH32S72APHB-6 Datasheet PDF - Mitsubishi Electric Semiconductor

Part No. MH32S72APHB-6
Download  MH32S72APHB-6 Click to view

File Size   703.35 Kbytes
Page   55 Pages
Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Description 2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM

MH32S72APHB-6 Datasheet (HTML) - Mitsubishi Electric Semiconductor

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MH32S72APHB-6 Product details

DESCRIPTION
The MH32S72APHB is 33554432 - word by 72-bit Synchronous DRAM module. This consists of eighteen industry standard 16Mx8 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP.
The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required.
This is a socket type - memory modules, suitable for easy interchange or addition of modules.

FEATURES
• Utilizes industry standard 16M x 8 Sy nchronous DRAMs TSOP and industry standard EEPROM in TSSOP
• 168-pin (84-pin dual in-line package)
• single 3.3V±0.3V power supply
• Max. Clock frequency -6:133MHz,-7,8:100MHz
• Fully synchronous operation referenced to clock rising edge
• 4 bank operation controlled by BA0,1(Bank Address)
• /CAS latency- 2/3(programmable)
• Burst length- 1/2/4/8/Full Page(programmable)
• Burst type- sequential / interleave(programmable)
• Column access - random
• Auto precharge / All bank precharge controlled by A10
• Auto refresh and Self refresh
• 4096 refresh cycle /64ms
• LVTTL Interface
• Discrete IC and module design conform to PC100/PC133 specification.

APPLICATION
   PC main memory



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