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MH32D72AKLB-75 Datasheet (PDF) - Mitsubishi Electric Semiconductor

MH32D72AKLB-75 Datasheet PDF - Mitsubishi Electric Semiconductor
Part No. MH32D72AKLB-75
Download  MH32D72AKLB-75 Click to view

File Size   358.03 Kbytes
Page   40 Pages
Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Description 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MH32D72AKLB-75 Datasheet (PDF)

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MH32D72AKLB-75 Datasheet PDF - Mitsubishi Electric Semiconductor

Part No. MH32D72AKLB-75
Download  MH32D72AKLB-75 Click to view

File Size   358.03 Kbytes
Page   40 Pages
Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Description 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MH32D72AKLB-75 Datasheet (HTML) - Mitsubishi Electric Semiconductor

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MH32D72AKLB-75 Product details

DESCRIPTION
The MH32D72AKLB is 33554432 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 18 industry standard 16M x 8 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory module is suitable f or main memory in computer systems and easy to interchange or add modules.

FEATURES
- Utilizes industry standard 16M X 8 DDR Synchronous DRAMs in TSOP package , industry standard Registered Buffer in TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data
- Dif f erential clock inputs (CK0 and /CK0)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cycles /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-9
- SSTL_2 Interf ace
- Module 2bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge

APPLICATION
   Main memoryunit for PC, PC server, Server, W S.



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