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MH32D64KQH-10 Datasheet (PDF) - Mitsubishi Electric Semiconductor

MH32D64KQH-10 Datasheet PDF - Mitsubishi Electric Semiconductor
Part # MH32D64KQH-10
Download  MH32D64KQH-10 Download

File Size   350.7 Kbytes
Page   40 Pages
Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Description 2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module

MH32D64KQH-10 Datasheet (PDF)

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MH32D64KQH-10 Datasheet PDF - Mitsubishi Electric Semiconductor

Part # MH32D64KQH-10
Download  MH32D64KQH-10 Click to download

File Size   350.7 Kbytes
Page   40 Pages
Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Description 2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module

MH32D64KQH-10 Datasheet (HTML) - Mitsubishi Electric Semiconductor

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MH32D64KQH-10 Product details

DESCRIPTION
The MH32D64KQH is 33554432 - word x 64-bit Double Data Rate(DDR) Synchronous DRAM mounted module.
This consists of 8 industry standard 32M x 8 DDR Synchronous DRAMs in TSOP with SSTL_2 interf ace which achieves very high speed data rate up to 133MHz.
This socket-type memory module is suitable for main memory in computer systems and easy to interchange or add modules.

FEATURES
- Utilizes industry standard 32M X 8 DDR Synchronous DRAMs in TSOP package , industry standard EEPROM(SPD) in TSSOP package
- 200pin SO-DIMM
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positiv e CLK edge
- Data and data mask referenced to both edges of DQS
- 4bank operation controlled by BA0,BA1(Bank Address ,discrete)
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Ty pe - sequential/interleav e(programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms
- Auto refresh and Self ref resh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interface
- Module 1bank Configuration

APPLICATION
   Main memoryunit for Note PC, Mobile etc.




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